08-16-2017, 09:41 PM
A VHDL Primer
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Identifiers
An identifier in VHDL is composed of a sequence of one or more characters. A legal character is an upper-case letter (A.. Z), or a lower-case letter (a. .. z), or a digit (0 . . . 9) or the underscore ( _ ) character. The first character in an identifier must be a letter and the last character may not be an underscore. Lower-case and upper-case letters are considered to be identical when used in an identifier; as an example. Count, COUNT, and CouNT, all refer to the same identifier. Also,-two underscore characters cannot appear consecutively. Some more examples of identifiers are
Data Objects
A data object holds a value of a specified type. It is created by means of an object declaration. An example is
variable COUNT: INTEGER;
This results in the creation of a data object called COUNT which can hold integer values. The object COUNT is also declared to be of variable class.
Every data object belongs to one of the following three classes:
1. Constant: An object of constant cla^s can hold a single value of a given type. This value is assigned to the object before simulation starts and the value cannot be changed during the course of the simulation.
2. Variable: An object of variable class can also hold a single value of a given type. However in this case, different values can be assigned to the object at different times using a variable assignment statement.
3. Signal: An object belonging to the signal class has a past history of values, a current value, and a set of future values. Future values can be assigned to a signal object using a signal assignment statement
Other Ways to Declare Objects
Not all objects in a VHDL description are created using object declarations. These other objects are declared as
1. ports of an entity. All ports are signal objects.
2. generics of an entity (discussed in Chap. 7). These are constant objects.
3. formal parameters of functions and procedures (discussed in Chap. 8). Function parameters are constant objects or signal objects while procedure parameters can belong to any object class,
4. a file declared by a file declaration (see file types in next section).
There are two other types of objects that are implicitly declared. These are the indices of a for. . . loop statement and the generate statement (generate statements are discussed in Chap. 10). An example of such an implicit declaration for the loop index in a for. . . loop statement is shown.
Data Types
Every data object in VHDL can hold a value that belongs to a set of values. This set of values is specified by using a type declaration. A type is a name that has associated with it a set of values and a set of operations. Certain types, and operations that can be performed on objects of these types, are predefined in the language. For example, INTEGER is a predefined type with the set of values being integers in a specific range provided by the VHDL system. The minimum range that must be provided is -(2^31 - 1) through +(2^31 - 1). Some of the allowable and frequently used predefined operators are +, for addition, -, for subtraction, /, for division, and *, for multiplication. BOOLEAN is another predefined type that has the values FALSE and TRUE, and some of its predefined operators are and, or, nor, nand, and not. The declarations for the predefined types of the language are contained in package STANDARD (see Appendix A); the operators for these types are predefined in the language.
[attachment=16012]
Identifiers
An identifier in VHDL is composed of a sequence of one or more characters. A legal character is an upper-case letter (A.. Z), or a lower-case letter (a. .. z), or a digit (0 . . . 9) or the underscore ( _ ) character. The first character in an identifier must be a letter and the last character may not be an underscore. Lower-case and upper-case letters are considered to be identical when used in an identifier; as an example. Count, COUNT, and CouNT, all refer to the same identifier. Also,-two underscore characters cannot appear consecutively. Some more examples of identifiers are
Data Objects
A data object holds a value of a specified type. It is created by means of an object declaration. An example is
variable COUNT: INTEGER;
This results in the creation of a data object called COUNT which can hold integer values. The object COUNT is also declared to be of variable class.
Every data object belongs to one of the following three classes:
1. Constant: An object of constant cla^s can hold a single value of a given type. This value is assigned to the object before simulation starts and the value cannot be changed during the course of the simulation.
2. Variable: An object of variable class can also hold a single value of a given type. However in this case, different values can be assigned to the object at different times using a variable assignment statement.
3. Signal: An object belonging to the signal class has a past history of values, a current value, and a set of future values. Future values can be assigned to a signal object using a signal assignment statement
Other Ways to Declare Objects
Not all objects in a VHDL description are created using object declarations. These other objects are declared as
1. ports of an entity. All ports are signal objects.
2. generics of an entity (discussed in Chap. 7). These are constant objects.
3. formal parameters of functions and procedures (discussed in Chap. 8). Function parameters are constant objects or signal objects while procedure parameters can belong to any object class,
4. a file declared by a file declaration (see file types in next section).
There are two other types of objects that are implicitly declared. These are the indices of a for. . . loop statement and the generate statement (generate statements are discussed in Chap. 10). An example of such an implicit declaration for the loop index in a for. . . loop statement is shown.
Data Types
Every data object in VHDL can hold a value that belongs to a set of values. This set of values is specified by using a type declaration. A type is a name that has associated with it a set of values and a set of operations. Certain types, and operations that can be performed on objects of these types, are predefined in the language. For example, INTEGER is a predefined type with the set of values being integers in a specific range provided by the VHDL system. The minimum range that must be provided is -(2^31 - 1) through +(2^31 - 1). Some of the allowable and frequently used predefined operators are +, for addition, -, for subtraction, /, for division, and *, for multiplication. BOOLEAN is another predefined type that has the values FALSE and TRUE, and some of its predefined operators are and, or, nor, nand, and not. The declarations for the predefined types of the language are contained in package STANDARD (see Appendix A); the operators for these types are predefined in the language.