08-16-2017, 08:46 PM
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INTRODUCTION
A PLL circuit is used to synchronize an output signal, which is usually generated by an oscillator, with a reference or input signal in frequency as well as in phase. In the synchronized state, the difference (error) between the reference and the oscillator output is zero or at least very small. So it is called locked
The phase-lock-loop (PLL) is commonly used in microprocessors to generate a clock at high frequency ( F out = 2GHz for example) from an external clock at low frequency ( F ref = 100MHz for example) . The PLL is also used as a clock recovery circuit to generate a clock signal from a series of bit transmitted in serial without synchronization clock.
The PLL uses a high frequency oscillator with varying speed, a counter, a phase detector and a filter. The PLL includes a feedback loop which lines up the output clock Clk Out with the input clock Clk In through a phase locking stabilization process. When locked, the high input frequency f out is exactly N* fin as shown in figure.1. A variation of the input frequency fin is transformed by the phase detector into a pulse signal which is converted in turn into variation of the analog signal Vc .This signal changes the VCO frequency which is divided by the counter and changes clk Div according to fin.
Component description:
The PLL circuit consists of three main parts.
1. The phase & frequency detector
2. LF (loop filter)
3. VOC (voltage control oscillator)
PHASE AND FREQUENCY DETECTOR
The first component in our DPLL is the phase and frequency detector. The output of the PFD depends on both the phase and frequency of the inputs. This type of phase detector is also termed a sequential phase detector. It compares the leading edges of data and data1 (data is the input signal to PFD, data1 is considered as the feedback signal from the output of VCO to PFD). A data1 rising edge cannot be present without a data rising edge. If the rising edge of the data leads the data1 rising edge, the "Up" output of the phase detector goes high while the "Down" output remains low. This causes the data1 frequency to increase and makes the edges move closer. If the data1 signal leads the data, "Up" remains low while the "Down" goes high. And we can find the phase difference between data1 and data.
There are several characteristic of PFD which can be described as below:
1. A rising edge from the data and data1 must be present when doing a phase comparison
2. The width of the data1 and the data is irrelevant.
3. The output of the "Up" and "Down" of the PFD are both low when the circuit is locked. It Will cause the output of the filter a constant value.
LOOP FILTERS:
The second component in our DPLL is the loop filter. In our circuit, the loop filter consists of two parts: the charge pump and the RC-filter. The output of the PFD should be combined into a single output to drive the loop filter. In our project, we use the charge pump to implement it. In charge pump, two NMOS and two PMOS are connected serially. The uppermost PMOS and lowermost NMOS are considered as the current source and the other PMOS and NMOS in the middle are connected to the "Up" and "Down" of the output of PFD, respectively (Be careful that the PMOS in the middle is not connected with "Up" directly. There is an inverter between them). When the PFD "Up" signal goes high, the PMOS will turn on (because that the signal from the inverter goes low). This will connect the current source to the loop filter. It is in the similar way when the PFD" Down" signal goes high.
The loop filter is a simple RC filter, However, it plays a very important role in the DPLL. Unless the loop filter values are correctly chosen, it would take the loop too long to lock or once locked it is still "unstable" -- small variations in the input data may cause the loop unlock again.
If the rising edge of data leads that of data1, the PFD "Up" goes high. And it will cause the voltage of the output signal of the loop filter become higher. If the rising edge of data lags that of data1, the PFD "Down" goes high. It would cause output signal of the loop filter become lower.
INTRODUCTION
A PLL circuit is used to synchronize an output signal, which is usually generated by an oscillator, with a reference or input signal in frequency as well as in phase. In the synchronized state, the difference (error) between the reference and the oscillator output is zero or at least very small. So it is called locked
The phase-lock-loop (PLL) is commonly used in microprocessors to generate a clock at high frequency ( F out = 2GHz for example) from an external clock at low frequency ( F ref = 100MHz for example) . The PLL is also used as a clock recovery circuit to generate a clock signal from a series of bit transmitted in serial without synchronization clock.
The PLL uses a high frequency oscillator with varying speed, a counter, a phase detector and a filter. The PLL includes a feedback loop which lines up the output clock Clk Out with the input clock Clk In through a phase locking stabilization process. When locked, the high input frequency f out is exactly N* fin as shown in figure.1. A variation of the input frequency fin is transformed by the phase detector into a pulse signal which is converted in turn into variation of the analog signal Vc .This signal changes the VCO frequency which is divided by the counter and changes clk Div according to fin.
Component description:
The PLL circuit consists of three main parts.
1. The phase & frequency detector
2. LF (loop filter)
3. VOC (voltage control oscillator)
PHASE AND FREQUENCY DETECTOR
The first component in our DPLL is the phase and frequency detector. The output of the PFD depends on both the phase and frequency of the inputs. This type of phase detector is also termed a sequential phase detector. It compares the leading edges of data and data1 (data is the input signal to PFD, data1 is considered as the feedback signal from the output of VCO to PFD). A data1 rising edge cannot be present without a data rising edge. If the rising edge of the data leads the data1 rising edge, the "Up" output of the phase detector goes high while the "Down" output remains low. This causes the data1 frequency to increase and makes the edges move closer. If the data1 signal leads the data, "Up" remains low while the "Down" goes high. And we can find the phase difference between data1 and data.
There are several characteristic of PFD which can be described as below:
1. A rising edge from the data and data1 must be present when doing a phase comparison
2. The width of the data1 and the data is irrelevant.
3. The output of the "Up" and "Down" of the PFD are both low when the circuit is locked. It Will cause the output of the filter a constant value.
LOOP FILTERS:
The second component in our DPLL is the loop filter. In our circuit, the loop filter consists of two parts: the charge pump and the RC-filter. The output of the PFD should be combined into a single output to drive the loop filter. In our project, we use the charge pump to implement it. In charge pump, two NMOS and two PMOS are connected serially. The uppermost PMOS and lowermost NMOS are considered as the current source and the other PMOS and NMOS in the middle are connected to the "Up" and "Down" of the output of PFD, respectively (Be careful that the PMOS in the middle is not connected with "Up" directly. There is an inverter between them). When the PFD "Up" signal goes high, the PMOS will turn on (because that the signal from the inverter goes low). This will connect the current source to the loop filter. It is in the similar way when the PFD" Down" signal goes high.
The loop filter is a simple RC filter, However, it plays a very important role in the DPLL. Unless the loop filter values are correctly chosen, it would take the loop too long to lock or once locked it is still "unstable" -- small variations in the input data may cause the loop unlock again.
If the rising edge of data leads that of data1, the PFD "Up" goes high. And it will cause the voltage of the output signal of the loop filter become higher. If the rising edge of data lags that of data1, the PFD "Down" goes high. It would cause output signal of the loop filter become lower.