08-16-2017, 10:31 PM
Abstract - This paper presents a novel FPGA implementation of a two dimensional (8x8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 million multiplications or additions per second.
Presented By:
D.W. Trainor
J.P. Heron* and R.F. Woods
1. INTRODUCTION.
There has been considerable interest in implementing DSP algorithms using FPGA technology. Examples include the Altera Megafunction Partners Program [1] and examples from Xilinx [2]. However, FPGA solutions are typified by poor hardware utilisation and solutions dominated by routing. This is due to the variety of FPGA structures e.g. PAL based, etc.. and the fact that little account is given to developing a suitable architectural description of the algorithm for the specific FPGA technology.
Presented By:
D.W. Trainor
J.P. Heron* and R.F. Woods
1. INTRODUCTION.
There has been considerable interest in implementing DSP algorithms using FPGA technology. Examples include the Altera Megafunction Partners Program [1] and examples from Xilinx [2]. However, FPGA solutions are typified by poor hardware utilisation and solutions dominated by routing. This is due to the variety of FPGA structures e.g. PAL based, etc.. and the fact that little account is given to developing a suitable architectural description of the algorithm for the specific FPGA technology.