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Clock-Tree Power Optimization based on RTL Clock-Gating - santosh4048 - 08-17-2017 ABSTRACT As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing clock power based on clock gating. We present a methodology that, starting from an RTL description, automatically generates a set of constraints for driving the construction of the clock tree by the clock synthesis tool. The methodology has been fully integrated into an industry-strength design flow, based on Synopsys DesignCompiler (front-end) and Cadence Silicon Ensemble (back-end). The power savings achieved on some industrial examples show that, when the size of the circuits is significant, savings on the power consumption of the clock tree are up to 75% larger than those achieved by applying traditional clock gating at the clock inputs of the RTL modules of the designs. Categories and Subject Descriptors B.5 [Hardware]: Register-Transfer-Level Implementation; B.6 [Hardware]: Logic Design; B.7 [Hardware]: Integrated Circuits General Terms Design Keywords Low-power design, clock-tree synthsis 1. INTRODUCTION The clock distribution network normally accounts for more than 40% of the total power budget of a CMOS circuit, as the clock nets operate at the highest switching frequency of any other signal and they drive a large fanout. Designing the clock tree is thus critical not only for performance, but also for power. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC 2003, June 2-6, 2003, Anaheim, California, USA. Copyright 2003 ACM 1-58113-688-9/03/0006 ..$5.00. Early work on clock tree synthesis focused on the generation of zero-skew trees [10] or minimum wire-length [4] clock distribution networks. More recently the area of low power clock tree synthesis has been investigated. In [5], the authors proposed an approach based on reduced voltage swings, while in [3] power savings on the clock network were obtained by taking advantage of interconnection parasitic inductance. Also, solutions based on powerconstrained buffer insertion and simultaneous buffer and clock wire sizing can provide significant savings [11, 2, 1]. Although these techniques are effective, none of them considers that clock signals are not always needed, and thus power can be saved by masking off (i.e., gating) the clock when circuits are idle. Clock gating can significantly reduce the switching activity in a circuit and on clock nets; thus, it has been viewed as one of the most effective logic, RTL and architectural approaches to power minimization. Unfortunately, if applied in a uncontrolled fashion, gating can adversely impact clock power. In fact, in order to amortize its power and area overhead, clock-gating logic should be shared among several flip-flops. If the flip-flops that share a common gated clock (i.e., a gated-clock domain) are widely dispersed across the chip, a significant wiring overhead is induced in the clock distribution network, as each domain must be independently distributed on dedicated wires. As a result, clock drivers in each domain are loaded with a much larger capacitance and power may increase even if switching activity is decreased [6, 9]. We then conclude that clock gating and clock tree construction should not be seen as two independent steps and a synergistic strategy is needed. Several authors have focused on this problem in the recent past. In the sequel, we briefly summarize two contributions that have some common roots with the approach we propose in this paper. Download full report http://googleurl?sa=t&source=web&cd=1&ved=0CBcQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.10.5806%26rep%3Drep1%26type%3Dpdf&ei=EUAyTujyDYfZrQf27I3MCw&usg=AFQjCNEqg1hvMzCQBsXFY-YKUzgsf1dSCw&sig2=fH1tHbt5-_K6VG53B4mHDQ |