08-16-2017, 10:14 PM
1. The Design and FPGA Implementation of GF (2128 ) Multiplier for Ghash
2. Spread Spectrum Image Watermarking with Digital Design
3. FPGA Implementation of Viterbi Decoder IEE 200
4. A Full Adder Based Methodology for the Design of Scaling Operation in Residue Number System IEE 2008
5. Efficient On Chip Crosstalk Avoidance CODEC Design
6. Fault Secure Encoder and Decoder for Memory Applications
7. Hardware implementation of Variable Precision Multiplication on FPGA
8. A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
9. Asynchronous Computing in Sense Amplifier based Pass Transistor Logic IEE 2008
10. Novel Area Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
11. Fast Enhancement of Validation Test Sets for Improving the Stuck at Fault Coverage of RTL Circuits
12. A Compact AES Encryption Core on Xilinx FPGA
13. Soft Error Tolerance and Mitigation in Asynchronous Burst Mode Circuits
14. Left to Right Serial Multiplier for Large Numbers on FPGA
15. A VLSI Progressive Coding for Wavelet based Image Compression
16. A Generalization of a Fast RNS Conversion for a New 4 Modulus Base
17. A Low Power Low Area Multiplier Based on Shift and Add Architecture
18. Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST
19. Design and Implementation of a Field Programmable CRC Circuit Architecture
20. Designing Efficient Online Testable Reversible Adders with New Reversible Gate
21. Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency
22. A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S Box Architecture
23. Superscalar Power Efficient Fast Fourier Transform FFT Architecture
24. A New Low Power Test Pattern Generator Using a Variable Length Ring Counter
25. Deviation Based LFSR Reseeding for Test Data Compression
26. A Novel Multiplexer based truncated array multiplier
27. VLSI Design of Diminished One Modulo 2n + 1 Adder Using Circular Carry Selection
28. Design of Network on Chip Architectures with a Genetic Algorithm Based Technique