08-17-2017, 12:32 AM
A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter
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1. Introduction
Built-in Self-Test (BIST) is a design-for-test (DFT)
technique in which testing is achieved through built-in
hardware features. The steps in a typical BIST approach are:
(1) on-chip test pattern generation; (2) application of
patterns to the circuit under test (CUT); (3) analysis of CUT
responses via on-chip output response analyzer (ORA) and
(4) making decision whether chip is faulty or not. Efficient
TPG design is related to the step (1) and it is an important
subject in BIST. Generation of test vector sequences with
high fault coverage in minimal hardware size and testing
time is the main objective [l, 2].
Motivation example
In this section, we d like to illustrate the basic idea of
input-division technique through a simple example. The
circuit diagram of this example is shown in Fig. 1. It is
composed of a 3-input AND gate and a 2-input OR gate
with their outputs ANDed together. As shown in Table 1 the
size of the collapsed fault list is 18. Test vectors for each
fault are listed under left column and they, as a whole,
constitute the complete test set for the circuit.
Uniform cluster analysis
Cluster analysis is used for numerical classification in
many fields [8,9]. We use a uniform clustering algorithm
based on BDD for the inputs grouping. The test set is first
represented as a graph, to which the proposed algorithm is
applied. In the graph, each node denotes a column of the test
set. The basic idea is to first view each node in the graph as
a cluster, then continuously merge pairs of similar clusters
until a predefined threshold is reached. This threshold can
be either the number of the vectors which contain the samebit-
sequence, referred to as MinVectorNum.
Architecture
Twisting-ring counter (TRC) and ring counter (RC) are
commonly used as deterministic BIST TPG, because it can
build with the simple and uniform BIST control logic.
Suppose that if all inputs of the CUT are configured into a
TRC/RC, it will subsequently cause more transitions.
Fortunately, we discover that the identical sequences often
appear in many test patterns that are applied to CUT. Based
on the observation, a variable-length RC BIST TPG is
proposed in this paper. In this proposed scheme, all inputs
are divided into two groups.
Summary and conclusions
A BIST TPG which can highly reduce power
consumption during test application is proposed. The power
consumption reduction is achieved by furthest freezing
some inputs of the CUT. The proposed 2PRC-TPG consists
of a variable-length RC and some control logic. For each
seed, the inputs of CUT are divided into two groups (partialacting-
inputs and partial-freezing-inputs). During testing,
the partial-acting-inputs are reconfigured into a short RC,
and the partial-freezing-inputs are frozen, and keep their
values unchanged. Experimental results show that the
proposed BIST scheme based on the 2PRC-TPG can
efficiently reduce the data storage, test time, the peak power
and the total power consumption during testing with a small
size decoding logic. Moreover, these results are obtained
with no loss of stuck-at fault coverage (FC).