Low Power, Energy- efficient Domino Logic Circuits

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Low Power, Energy- efficient Domino Logic Circuits

Salendra.Govindarajulu1, Dr.T.Jayachandra Prasad2
1Associate Professor, ECE, RGMCET, JNTU

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Abstract
Sub-threshold leakage power is soon expected to dominate the total power consumed by a CMOS circuit in deep submicron ( DSM ) technology. Circuit techniques aimed at lowering leakage currents are therefore highly desirable. In this work, low power CMOS designs using dual threshold voltage ( dual-Vt ) domino logic are proposed. Single threshold voltage ( single-Vt ), standard dual-Vt and modified dual-Vt domino logic circuits regarding power and speed are compared. These design styles are compared by performing detailed transistor-level simulations on bench mark circuits using DSCH3 and Microwind3 CAD tool.