Low Power Multiplier Implementation full report

[piyush kumar pushkar]

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Abstract
There are different entities that one would like to optimize when designing a VLSI circuit. These entities can often not be optimized simultaneously, only improve one entity at the expense of one or more others The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern VLSI design field. In Very Large Scale Integration, Low power VLSI design is necessary to meet MOORE S law and to produce consumer electronics with more back up and less weight. Multiplication occurs frequently in finite impulse response filters, fast Fourier transforms, discrete cosine transforms, convolution, and other important DSP and multimedia kernels. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation. The proposed high speed low power multiplier can attain 30% speed improvement and 22% power reduction in the modified booth encoder when compared with the conventional array multipliers.

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Presented By:
C. N.Marimuthu1, P. Thangaraj2,

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Read full report
http://icgstpdcs/Volume8/Issue1/P1170845463.pdf

[mayank]

Abstract
A novel reconfigurable low-power high-performance matrix multiplier architecture and its component circuits are described in this article. The processor can be simply reconfigured to calculate the product of matrices X[n,K] and Y[k,m] where n, k, m are integers and b being the precision which ranges from 4 to 64 bits and maximizing the utilization of the hardware available. To illustrate this , the hardware equivalent to one 64 64 bit high precision multiplier can be reconfigured to produce the product of two matrices X8 8 and Y8 8 of 8-bit items in 9 pipeline cycles. The matrix multiplier of size s may consist of an array of (s/m)^2 of m m. may consist of an array of (s/m)2 of m m small multipliers utilized in the design.

A Reconfigurable Low-power High-Performance Matrix Multiplier Architecture With Borrow Parallel Counters Counters

The Partial Product Decomposition-Based Arithmetic Architecture:Here the The 4x4 partial product matrix, the addition of the partial product bits, multiplication of two 8-bit numbers using four 4x4 multipliers etc have been shown.Utilizing partial product bit matrix decomposition for full self-testability, Utilizing borrow bits for simple circuit and high speed, more importantly, reducing pass-transistor path length (no more than 4) and rearranging and balancing input bits to each column of small multipliers are done. For more info refer these:
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[hanamaraddi1]

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[subins2]

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[rachana raghu]

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