Accelerating Matrix Operations with Improved Deeply Pipelined Vector Reduction

[ravi0537`]

Abstract This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Unlike the Spidergon network, the SD network which extends the Spidergon network into the second dimension, significantly reduces the network diameter, well below the popular 2D Mesh and Torus networks for one extra node degree and roughly 25 percent more links. A detailed construction of the SD network and a method to reshuffle the SD network's nodes for layout onto the 2D plane, and simple one-to-one and broadcast routing algorithms for the SD network are presented. The various configurations of the SD network are analyzed and compared including detailed area and delay studies. To interconnect a thousand cores, the paper concludes that a hybrid version of the SD network with smaller SD instances interconnected by a crossbar is a feasible low-diameter network topology for interconnecting the cores of a thousand core system.
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[siju]

abstract Many scientific or engineering applications involve matrix operations, in which reduction of vectors is a common operation. If the core operator of the reduction is deeply pipelined, which is usually the case, dependencies between the input data elements cause data hazards. To tackle this problem, we propose a new reduction method with low latency and high pipeline utilization. The performance of the proposed design is evaluated for both single data set and multiple data set scenarios. Further, QR decomposition is used to demonstrate how the proposed method can accelerate its execution. We implement the design on an FPGA and compare its results to other methods
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Phone : +91-9618855666
+91-8008855666
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