10-04-2017, 09:02 PM
Designing A SEPIC Converter
[attachment=68]
Introduction
In a SEPIC (Single Ended Primary Inductance Converter) design,
the output voltage can be higher or lower than the input
voltage. The SEPIC converter shown in Figure 1 uses two
inductors, L1 and L2. The two inductors can be wound on the
same core since the same voltages are applied to them
throughout the switching cycle. Using a coupled inductor
takes up less space on the PCB and tends to be lower cost
than two separate inductors. The capacitor Cs isolates the
input from the output and provides protection against a shorted
load. Figures 2 and 3 show the SEPIC converter current
flow and switching waveforms.
Inductor Selection
A good rule for determining the inductance is to allow the
peak-to-peak ripple current to be approximately 40% of the
maximum input current at the minimum input voltage. The
ripple current flowing in equal value inductors L1 and L2 is
given by:
Power MOSFET Selection
The parameters governing the selection of the MOSFET are
the minimum threshold voltage Vth(min), the on-resistance RDS
(ON), gate-drain charge QGD, and the maximum drain to source
voltage, VDS(max). Logic level or sublogic-level threshold
MOSFETs should be used based on the gate drive voltage.
Output Capacitor Selection
In a SEPIC converter, when the power switch Q1 is turned on,
the inductor is charging and the output current is supplied by
the output capacitor. As a result, the output capacitor sees
large ripple currents. Thus the selected output capacitor must
be capable of handling the maximum RMS current. The RMS
current in the output capacitor is:
Input Capacitor Selection
Similar to a boost converter, the SEPIC has an inductor at the
input. Hence, the input current waveform is continuous and
triangular. The inductor ensures that the input capacitor sees
fairly low ripple currents. The RMS current in the input capacitor
is given by: