08-17-2017, 12:15 AM
Introduction
I.a. Objectives
In this experiment, parallel adders, subtractors and complementors will be
designed and investigated. In the first and second parts of the experiment you will
implement your circuits using ICs and connecting them on the breadboard. In the
rest of the experiment, you will use Quartus 14.1 software and FPGA to
implement the circuits. In this experiment, you need to download your designs to
the FPGA and check the results by physical means, i.e., using LEDs and
oscilloscope. Another objective of this experiment is to expose you the
hierarchical design method for logic circuits.
I.b. Background
Digital computers perform a number of arithmetic operations for information
processing. These tasks are performed using various arithmetic logic circuits. The
most commonly used basic arithmetic circuits are adders, subtractors and
complementors. A short description of these circuits is given below.
Adders:
Adders are divided into two groups: half adders and full adders. Full adders are
used to add three bits where one of them is carry from the preceding adder. They
have two outputs: sum and carry to the next stage. In half adders, only two inputs
are considered as operands; hence carry inputs are ignored. The truth table of a
full adder is given in Table Two of the input variables, denoted by Xk and Yk,
represent two significant bits to be added. The third input, Ck-1 represents the
carry from the previous lower significant position.
