10-04-2017, 07:23 PM
Abstract
As the microprocessor speed increases from 500MHz to 1GHz and beyond, the designers must find new ways to make the cache memory for high speed access. Here, the clock to wordline path delay is optimized using a novel circuit
design technique. The delay is optimized by about 2.5 times at worst
case corner. Considering a memory element whose access time is 800ps and read and write operation occurs simultaneously in the same clock cycle, 18% improvement of the overall access time is observed. There is also a pre-decoding and post-decoding discussion in which the best pre-decoding and post-decoding schemes based on minimum pre-decoded lines, minimum stack
size in post decoder and maximum granularity of x-decoders is done.
Decoding Schemes
In a RAM chip, the row and column to be selected are determined by
decoding binary address information. an n-bit decoder for row selection has 2^n output lines out of which one will be activated. The column decoder takes m inputs and produce a 2^m bit acces signal. A multiplexer circuit is used for the selection of the particular row or column. An n-bit decoder requires 2^n decoding levels. higher delays are caused by using such large number of gates. The use of multiple
stages of decoding may reduce the delay. pre-decoding is used in control block which generates
predecoded signals. These pre-decoded signals are used in the final
post decoding stages of xdecoders.
Get the full report here:
http://filesonicfile/23656391/A Novel Circuit to Optimize Access Time and Decoding Schemes in Memories.pdf