Assessment of SET Logic Robustness Through Noise Margin Modeling

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Assessment of SET Logic Robustness Through Noise Margin Modeling

Chaitanya Sathe, Surya Shankar Dan, and Santanu Mahapatra, Member, IEE

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Abstract
A compact model for noise margin (NM) of single electron transistor (SET) logic is developed, which is a function of device capacitances and background charge ( ). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (CG and CT ). It is shown that choosing = CT /CG = 1/3maximizes the NM. An estimate of the maximum tolerable is shown to be equal to 0.03e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation. Index Terms Background charge, compact model, Coulomb blockade, noise margin (NM), single-electron transistor (SET).