08-16-2017, 09:19 PM
Abstract
In this paper, we review the logical effort model presented in [1]. Based on the HSPICE simulation results using 0.18/Jm, CMOS technology as applied to logic blocks used in arithmetic circuits; we analyze the efficiency of the model and also present modifications that include modeling of wire delay. We propose a new model for logical effort that will better fit the behavior of these blocks. The results are applicable for evaluation of arithmetic units as well as for development of new arithmetic algorithms. Our ultimate objective is to close the gap between arithmetic algorithms and their performance in VLSI CMOS.
Presented By:
Xiao Yan Yu*,**, Vojin G. Oklobdzija*,** * ACSEL Laboratory Electrical and Computer Engineering Department University of California, Davis
William W. Walker** **Advanced LSI Research Fujitsu Laboratory of America Sunnyvale, California
1. Introduction
Sutherland and Sproull [1] presented a simple logical effort (LE) delay model d = z(gXh + Pinv), where x is the intrinsic delay of an inverter, g is the logical effort of the gate or how well the gate drives current in compare to a minimal sized inverter, which is the ratio of the on-resistance of the gate to the on-resistance of an inverter with the same input capacitance, h is the electrical effort of the gate, which is the ratio of load capacitance to input capacitance, and zP,nv is the parasitic delay of the gate. After unnormalizing, the delay model for LE can be seen to be simply d = ?0 + R.X.Cload where to is the intrinsic delay of the gate, which is equivolent to zP^,, R is its on-resistance value and Cioaa is the load capacitance. Table 1 provides a list of theoretical logical effort values for NAND and NOR gates assuming the optimal ratio of PMOS tran'sistor size to NMOS transistor size is 2 for an inverter.
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http://citeseerx.ist.psu.edu/viewdoc/dow...1&type=pdf