FinFET Technology

[nijesh.m.t]

[attachment=7410]

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Seminar on finFET technology

c0ntents
INTRODUCTION
PARTIALLY DEPLETED SOI

PARASITIC BIPOLAR EFFECT

SCALING FROM PD SOI TO FD SOI

MAJOR DESIGN ISSUES
FEATURES OF FINFET
PROCESS FLOW OF FINFET

APPLICATIONS OF FINFET

SIMULATION RESULTS
CONCLUSION
REFERENCES

Introduction:
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously.

The motivation behind this decrease is seen in high speed devices and in very large scale integrated circuits.

The limits most often cited are:-

control of the density.

finite subthreshold slope .

quantum-mechanical tunneling .

The channel depletion width must scale with the channel length to contain the off-state leakage I off
this leads:-

high doping concentration.

The gate oxide thickness tox must also scale with the channel length to maintain :-

gate control.

proper threshold voltage VT .

The thinning of the gate dielectric results in :-

gate tunneling leakage.

degrading the circuit performance.

power and noise margin.

Partially depleted(PD)SOI was the first SOI technology introduced for high performance microprocessor applications.

PARTIALLY DEPLETED [PD] SOI:
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide ( BOX ) layer
The device offers several advantages for performance/ power improvement:-

reduced junction capacitance.

Parasitic bipolar effect.

Hysteretic VT variation.

Dynamic loading effects.

MAJOR DESIGN ISSUES :
Gate Oxide Tunneling Leakage

Self heating

Soft Error Rate

Strained-Si channel And High-k Gate

Features of finFET:
Finfet consists of a vertical Si fin controlled by self_aligned double gate.

Main Features of Finfet are:-

Ultra thin Si fin for suppression of short channel effects

Raised source/drain to reduce parasitic resistance and improve current drive

Symmetric gates yield great performance,but can built asymmetric gates that target VT .

.
Finfets are designed to use multiple fins to achieve larger channel widths.

Source/Drain pads connect the fins in parallel.

As the number of fins is increased ,the current through the device increases.

.For eg: A 5 fin device 5 times more current than single fin device.

FinFET-DGCMOS Process Flow in Detail:
A conventional SOI wafer can be used as starting material for:-

Sacrificial oxidations.

Masked ion implantations.

specialized passive elements.

Gate deposition and etch.

APPLICATIONS OF FinFET:
DG devices like Fin FETs offer unique opportunities for microprocessor design.compared to a planar process in the same technology node,

FinFETs have reduced channel and gate leakage currents. This can lead to considerable power reductions when converting a planar design to fin FET technology.

Utilizing fin FETs would lead to a reduction in total power by a factor of two, without compromising performance.

Another possibility to save power arises when both gates can be controlled separately.

The second gate can be used to control the threshold voltage of the device, thereby allowing fast switching on one side and reduced leakage currents when circuits are idle.

Finally, separate access to both gates could also be used to design simplified logic gates.

This would also reduce power, and save chip area, leading to smaller, more cost-efficient designs. However chip designs using finFETs must cope with quantization of device width.

since every single transistor consists of an integral number of fins,each fin having the same height.

SIMULATION OF finFET USING DEVICE3D:
This article will present the simulation methodology of a self-aligned double-gate MOSFET structure (FinFET) using SILVACO 3-D simulation suite.

Device Features:-

A transistor is formed in a vertical ultra thin Si fin and is controlled by a double-gate, which considerably reduced short channel effects.

the two gates are self aligned and are aligned to S/D.

S/D is raised to reduce the access resistance.

Up to date gate process: low temperature, high -k dielectrics can be used .

Device Simulation:
The 3-D SILVACO simulation suite including Device3D, DevEdit3D and TonyPlot3D, allows device engineers to study deep sub-micron devices which are 3-D by nature like the FinFET presented above.

A 3-D FinFET structure was designed by using DevEdit3D. This is an advanced tool for structure editing and mesh generation.

CONCLUSION:

Simulations show that this structure should be scalable down to 10 nm.


This structure was fabricated by forming the S\D before the gate.

Further performance improvement is possible by using a thinner gate dielectric and thinner spacers.

FinFET is similar to the conventional MOSFET with regard to layout and fabrication.

. It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability.

Industrial research groups such as Intel, IBM and AMD have shown interests in developing similar devices, as well as mechanisms to migrate mask layouts from Bulk-MOS to FinFETs.

Design Issues such as high quality ultra thin fin lithography and source\drain resistance need to be resolved and a high-yield process flow needs to be established by process researchers before FinFETs can be used in commercial.

REFERENCES:
S. Thompson, P. Packan and M. Bohr, MOS scaling , Transistor challenges for the 21st century, Intel Tech.J.,vol.Q3 pp1-19,1998.

C.H.Wann, H. Noda, T. Tanaka, M.Yoshida and C. Hu, A comparative study of advanced MOSFET concepts , IEE Trans. Electron Devices, vol. 43, no. 10, pp 1742-1753, Oct. 1996

X. Huang, W.C. Lee, C.Kuo, D.Hisamoto, L. Chang, J. Keidzerski, E. Anderson, H.Takeuchi, Y.K. Choi, K.Asano.

.

[suchismita sahu]

[attachment=7586]

INTRODUCTION

Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.

Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications .Partially depleted (PD) SOI was the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential future technology/device choices.

In these device structures, the short-channel effect is controlled by geometry, and the off-state leakage is limited by the thin Si film. For effective suppression of the off-state leakage, the thickness of the Si film must be less than one quarter of the channel length.
The desired VT is achieved by manipulating the gate work function, such as the use of midgap material or poly-SiGe. Concurrently, material enhancements, such as the use of a) high-k gate material and b) strained Si channel for mobility and current drive improvement, have been actively pursued.

As scaling approaches multiple physical limits and as new device structures and materials are introduced, unique and new circuit design issues continue to be presented. In this article, we review the design challenges of these emerging technologies with particular emphasis on the implications and impacts of individual device scaling elements and unique device structures on the circuit design. We focus on the planar device structures, from continuous scaling of PD SOI to FD SOI, and new materials such as strained-Si channel and high-k gate dielectric.

PARTIALLY DEPLETED [PD] SOI

The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide ( BOX ) layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral floating body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT .

The device offers several advantages for performance/ power improvement:
1) reduced junction capacitance,
2) lower average threshold due to positive V BS during switching.
3) dynamic loading effects,in which the load device tends to be in high VT state during
switching
The performance comes at the cost of some design complexity resulting from the floating body of the device, such as
1) parasitic bipolar effect and
2) hysteretic VT variation.

Parasitic Bipolar Effect
In PDSOI an n-p-n transistor is formed with source and drain as emitter & collector respectively and body as the base. The topology typically involves an off transistor with the source and drain voltage set up in the high state (hence body voltage at high ) When the source is subsequently pulled down, large overdrive is developed across the body-source junction, causing bipolar current to flow through the lateral parasitic bipolar transistor.This may result in circuit failure.

In SRAM bitline structures, the aggregate parasitic bipolar effect of the unselected cells on the selected bitline disturbs the read/write operations and limits the number of cells that can be attached to a bitline pair
Hysteretic VT Variation
The hysteretic VT variation due to long time constants of various
body charging/discharging mechanisms.
A commonly used gauge for hysteretic VT variation (or history effect as it is known in the SOI community) is the disparity in the body voltages and delays between the so-called first switch and second switch . The first switch refers to the case where a circuit (e.g., inverter) starts in an initial quiescent state with input low and then undergoes an input-rising transition. In this case, the initial dc equilibrium body potential of the switching nMOSFET is determined primarily by the balance of the back-to-back drain-to-body and body-to-source diodes. The second switch refers to the case where the circuit is initially in a quiescent state with input high. The input first falls and then rises (hence, the name second switch ). For this case, the preswitch body voltage is determined by capacitive coupling between the drain and the body.

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[sanket_shevale]

FinFET Technology

Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high-speed devices and in very large-scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite sub threshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body.

The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.

Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications .Partially depleted (PD) SOIwas the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential "future" technology/device choices. In these device structures, the short-channel effect is controlled by geometry, and the thin Si film limits the off-state leakage. For effective suppression of the off-state leakage, the thickness of the Si film must be less than one quarter of the channel length. The desired VT is achieved by manipulating the gate work function, such as the use of midgap material or poly-SiGe. Concurrently, material enhancements, such as the use of a) high-k gate material and b) strained Si channel for mobility and current drive improvement, have been actively pursued. As scaling approaches multiple physical limits and as new device structures and materials are introduced, unique and new circuit design issues continue to be presented. In this article, we review the design challenges of these emerging technologies with particular emphasis on the implications and impacts of individual device scaling elements and unique device structures on the circuit design. We focus on the planar device structures, from continuous scaling of PD SOI to FD SOI, and new materials such as strained-Si channel and high-k gate dielectric.

Partially Depleted [PD] SOI
The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide ("BOX") layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral "floating" body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT. The device offers several advantages for performance/ power improvement:

1) Reduced junction capacitance,

2) Lower average threshold due to positive V BS during switching.

3) Dynamic loading effects, in which the load device tends to be in high VT state during switching The performance comes at the cost of some design complexity resulting from the floating body of the device, such as

1) Parasitic bipolar effect and

2) Hysteretic VT variation.

[balasubramani]

Definition
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high-speed devices and in very large-scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite sub threshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body.

The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.

Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications .Partially depleted (PD) SOIwas the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential "future" technology/device choices. In these device structures, the short-channel effect is controlled by geometry, and the thin Si film limits the off-state leakage. For effective suppression of the off-state leakage, the thickness of the Si film must be less than one quarter of the channel length. The desired VT is achieved by manipulating the gate work function, such as the use of midgap material or poly-SiGe. Concurrently, material enhancements, such as the use of a) high-k gate material and b) strained Si channel for mobility and current drive improvement, have been actively pursued. As scaling approaches multiple physical limits and as new device structures and materials are introduced, unique and new circuit design issues continue to be presented. In this article, we review the design challenges of these emerging technologies with particular emphasis on the implications and impacts of individual device scaling elements and unique device structures on the circuit design. We focus on the planar device structures, from continuous scaling of PD SOI to FD SOI, and new materials such as strained-Si channel and high-k gate dielectric.

Partially Depleted [PD] SOI
The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide ("BOX") layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral "floating" body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT. The device offers several advantages for performance/ power improvement:

1) Reduced junction capacitance,

2) Lower average threshold due to positive V BS during switching.

3) Dynamic loading effects, in which the load device tends to be in high VT state during switching The performance comes at the cost of some design complexity resulting from the floating body of the device, such as

1) Parasitic bipolar effect and

2) Hysteretic VT variation.

[shrijina]

Multigate device:A multigate device or Multiple Gate Field Effect Transistor(MuGFET) refers to a MOSFET which incorporates more than one gate into a single device.

FinFETs
This term refers to a nonplanar, double-gate transistor built on an SOI substrate. based on the earlier DELTA (single-gate) transistor design.This term was was coined by University of California, Berkeley researchers . In FinFETs the conducting channel is wrapped around a thin silicon "fin", which forms the body of the device.the effective channel length of the device is determined by the dimensions of the fin. AMD, IBM, and Motorola describe their double-gate development efforts as FinFET. any fin-based, multigate transistor architecture is described generically by the term FinFET regardless of number of gates. The Taiwan Semiconductor Manufacturing Company developed a 25-nm transistor operating on just 0.7 Volt . It has a gate delay of just 0.39 picosecond.
http://eetimesstory/OEG20021210S0002

[b]FinFET technology[\b]

FinFETs are seen as the most
likely candidate for the successor of the bulk CMOS from
the 22 nm node onwards, because of its compatibility with
the current CMOS technology.digital logic, SRAM, DRAM to Flash memory have all been demonstrated in FinFET. They have superior subthreshold
performance and excellent current saturation and as a result have applications in high-gain analog applications and in RF applications.

DEVICE FABRICATION:
-Processing of tall fin-structures:
very high
etching anisotropy is required to keep the fins narrow in the etching of tall fin-structures for for the highly-scaled devices.

-MOS devices on tall fins:
They are the FinFETs built on tall and narrow fin
structures. The
standard gate-stack with thermally-grown silicon-dioxide as the gate dielectric and LPCVD polysilicon as the gate
material.

for further details, refer this links:
http://en.wikipediawiki/Multigate_device#FinFETs
and refer this pdf too:

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[balaje]

The introduction of FinFET Technology has opened new chapters in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects.

It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability.

Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits.

The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body.

The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult.

The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.

[amrutha]

[attachment=5601]

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This article is presented by:
TAMAL DAS
ECE 4th

FIN-FET

Outline

Recent issues with scaling
Proposed solutions
Proposed Architectures

Recent issues with power crisis

FinFET Fabrication

FinFET Modeling

Conclusion
What is expected ?

Complexity
Delay
Power
Cost
Design Time
Size

Device Scaling

Channel Width Channel Length
To insure that optimal W/L ratios are available

Drain-to-Source Voltage Channel Length
To maintain a constant electric field from source to drain

Gate-Oxide Thickness Channel Length
To maintain control of the energy barrier in the channel through increasing the capacitive coupling from the gate

Channel Doping Density 1/(Channel Length)
Maintain a reasonable number of dopants in the decreasing channel area

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[amit12]

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[jonah7]

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