radix 8 booth multiplier verilog code

[sreekuttanss]

radix 8 booth multiplier verilog code

Abstract

Novel multi-modulus designs capable of performing the desired modulo operation for more than one modulus in Residue Number System (RNS) are explored in this paper to lower the hardware overhead of residue multiplication. Two multi-modulus multipliers that reuse the hardware resources amongst the modulo 2n-1, modulo 2n and modulo 2n+1 multipliers by virtue of their analogous number theoretic properties are proposed. The former employs the radix- 22 Booth encoding algorithm and the latter employs the radix- 23 Booth encoding algorithm. In the proposed radix- 22 and radix- 23 Booth encoded multi-modulus multipliers, the modulo-reduced products for the moduli 2n-1, 2n and 2n+1 are computed successively. With the basis of the radix- 22 Booth encoded modulo 2n+1 and radix- 23 Booth encoded modulo 2n-1 and modulo 2n+1 multiplier architectures, new Booth encoded modulo 2n multipliers are proposed to maximally share the hardware resources in the multi-modulus architectures. Our experimental results on {2n-1,2n,2n+1} based RNS multiplication show that the proposed radix- 22 and radix- 23 Booth encoded multi-modulus multipliers save nearly 60% of area over the corresponding single-modulus multipliers. The proposed radix- 22 and radix- 23 Booth encoded multi-modulus multipliers increase the delay of the corresponding single-modulus multipliers by 18% and 13%, respectively in the worst case. Compared to the single-modulus multipliers, the proposed multi-modulus multipliers incur a minor power dissipation penalty of 5%.