08-16-2017, 10:59 PM
IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD (AES)
(This is my Seventh Semister Major Project)
In the past, cryptography helped ensure secrecy in important communications, such as those of government covert operations, military leaders, and diplomats. Cryptography has come to be in widespread use by many civilians who do not have extraordinary needs for secrecy, although typically it is transparently built into the infrastructure for computing and telecommunications.
Advanced Encryption Standard (AES) is an algorithm for performing encryption (and the reverse, decryption) which is a series of well-defined steps that can be followed as a procedure. The original information is known as plaintext, and the encrypted form as cipher text. The cipher text message contains all the information of the plaintext message, but is not in a format readable by a human or computer without the proper mechanism to decrypt it; it resembles random gibberish to those not intended to read it. The encrypting procedure is varied depending on the key which changes the detailed operation of the algorithm. Without the key, the cipher cannot be used to encrypt or decrypt.
The Rijndael is a symmetric algorithm that encrypts variable size blocks with variable size keys. . The Advanced Encryption Standard (AES) specified a subset of Rijndael, fixing the block size on 128 bits. Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS-197), is an approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits, and this project implements the 128 bit standard using the VHDL, a hardware description language. The National Security Agency (NSA) announced that AES-128 may be used for classified information at the SECRET level and AES-192/256 for TOP SECRET level documents.
The algorithm consists of four stages that make up a round which is iterated 10 times for a 128-bit length key, 12 times for a 192-bit key, and 14 times for a 256-bit key. The first stage "SubBytes" transformation is a non-linear byte substitution for each byte of the block. The second stage "ShiftRows" transformation cyclically shifts (permutes) the bytes within the block. The third stage "MixColumns" transformation groups 4-bytes together forming 4-term polynomials and multiplies the polynomials with a fixed polynomial mod (x^4+1). The fourth stage "AddRoundKey" transformation adds the round key with the block of data.
The hardware implementation of AES could provide either high performance or low cost for specific applications. At backbone communication channels, or at heavily loaded server, it is not possible to lose processing speed running cryptography algorithms in general software, which drops the efficiency of the overall system. On the other side, a low cost and small design can be used in smart card applications, allowing a wide range of equipment to operate securely.
The design goal of this project is to create a demonstration of the AES-128 for the end user and not for integration into a communication or data storage device; however this design could be modified to such ends. The main objective of the project is to produce an optimized VHDL code for performance purpose, capable of achieving better performance than common software implementation.
The proposed project AES is implemented by using VHDL. The device is operated at 100.29 MHz when targeted to Spartan 3E.