08-16-2017, 08:53 PM
ABSTRACT
Existing SoC debug techniques mainly target bus-based systems. They are not readily applicable to the emerging system that use Network-on-Chip (NoC) as on-chip communication scheme. In this paper, we present the detailed design of a novel debug probe (DP) inserted between the core under debug (CUD) and the NoC. With embedded configurable triggers, delay control and time stamping mechanism, the proposed DP is very effective for inter-core transaction analysis as well as controlling embedded cores' debug processes. Experimental results show the functionality of the proposed DP and its area overhead
The Latest probe supports the latest Intel architecture, including the Intel Atom, Core2 Duo and Corei7 and uses a shielded, micro coaxial, impedance-controlled cable and connector system.The cable has been tested up to one meter for 100MHz JTAG operation and has been designed to let users operate in flexible configurations, including tight places. When changing to a different debug port, the probe instantly recognises the adapter and configures itself.