08-17-2017, 12:12 AM
Trends in Low-Power VLSI Design
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5.1 Introduction
As advances in lithography and fabrication of the N-type metal
oxide superconductor (NMOS) technology became possible in
the 1970s, the bipolar digital logic, transistor-transistor logic
(TTL) lost the battle in the digital design world for exactly the
same reasons that caused older technologies, such as the
vacuum tube technology, to retire. Circuits implemented in
the NMOS technology outperformed the corresponding TTL
circuits in terms of power dissipation. One of the main aspects
of power consumption is that it puts an upper limit on the
number of gates that can be reliably integrated on a single
package for any technology. As technology advanced, chips
grew, and it was possible to integrate more functions into
one chip. Just as for TTL, newer technology, called CMOS,
threatened to replace NMOS in the 1980s because CMOS
proved to consume even less power. With further advances in
technology and fabrication, the integration densities and the
rate at which chips operate have increased drastically, causing
power consumption to be of primary concern. In addition, the
new requirements set by device portability, reliability, and costs
have helped in alleviating the power consumption threat in
CMOS circuits. Because the power problem is getting more
Copyright 2005 by Academic Press.
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concerning, very large-scale integrated circuit (VLSI) designers
need to develop new efficient techniques to reduce the power
dissipation in current and future technologies, a task that is
full of challenges but yet exciting to explore.
5.2 Importance of Low-Power CMOS Design
With advances in CMOS technology, the potential packing
densities increase as the feature size of the MOS devices
shrinks, as shown in Figure 5.1. These increases and decreases
validate what Gordon Moore once said in the 1960s: the
number of transistors that can be integrated on a single die
would grow exponentially with time (Moore, 1965). The
example that amazingly proved his visionary prediction is
best illustrated by tracking the historical evolution of integrated
circuit (IC) design in the company he founded in
1972, Intel, and by using the trends in memory evolution.
Such observations are evident in Figure 5.2. Figure 5.2(A)
shows the trend in the IC logic complexity evolution for Intel
processors in the last two decades, whereas Figure 5.2(B) shows
the memory integration density as a function of time.
263
264 Tarek Darwish and Magdy Bayoumi
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FIGURE 5.1 Packing Density and Feature Size (A) The curve shows the past, current, and future trends for the feature size of the Intel
Processes. (B) This image shows a transistor laid out in the 0.09 micrometer or 90 nanometer technology. The gate for that transistor is 50nm.
© The transistor for future processors is shown here. Courtesy of Intel Corporation.
This increase in the number of transistors per package allowed
more functions to be integrated and increased the total logic
density of a chip. For example, Figure 5.3(A) indicates that the
logic density for the Intel microprocessors doubles every process
generation. At the same time, the frequency of operation has
dramatically increased due to the device scaling, Figure 5.3(B)
shows the introduction of performance boosting techniques,
such as pipelining, super-pipelining, and parallel architectures.
This increase in operating frequency was driven by the need for
fast digital systems realizing powerful personal workstations,
sophisticated computer graphics, and multimedia capabilities,
such as real-time speech recognition and real-time video (Chandrakasan
et al., 1992). When CMOS technology was introduced,
it was believed that the power consumption problem was solved.
The major concerns of the VLSI designer were mainly speed,
cost, and reliability; power consideration was mostly of secondary
importance (Pedram, 1995). But as major concerns were
being met, the power dissipated in a chip has increased from one
generation to another. Figure 5.4 shows the power dissipation of
the Intel family of microprocessors.
Figure 5.5 shows some projections for future processors if
power continues to dissipate at the same rate. The figure also
shows the power density behavior during the last two decades.
With the current processors, we have reached the power density
of a hot plate. Without limiting power dissipation, we will
someday have nuclear reactor-equivalent power dissipated in
chips we use at home or in our mobile devices!
Such observations are in contradiction with the scaling
theory. VLSI technology scaling has evolved at an amazingly
fast pace during the last 30 years; the minimum device size keeps
shrinking by a factor k = 0.7 per technology generation. The
basic scaling theory, known as constant field scaling mandates
the synergistic scaling of geometric features and silicon doping
levels to maintain a constant field across the gate oxide of the
MOS transistor (Benini et a l., 2001; Panasonic, 2000). According
to the constant field scaling theory, power dissipation scales as k 2
and power density (i.e., power dissipated per unit area) remains
constant while speed increases as k. Such contradiction between
the theory and conclusion from Figure 5.4 and Figure 5.5 has
two causes. First, die size has been steadily increasing with
technology (Figure 5.6), causing an increase in total average
power, as shown in Figure 5.4. Second, supply voltage has scaled
much more slowly than device size because supply voltage levels
have been standardized and because faster transistor operation
can be obtained for higher supply voltage levels.
Hence, this large amount of power dissipation is one of
the main motivations for VLSI designers to develop new
techniques to reduce the power consumed inside chips; power
5 Trends in Low-Power VLSI Design 265
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FIGURE 5.2 This Figure Shows the Number of Transistors Per Chip is Increasing. (A) Shows the number of transistors per Intel processor.
The horizontal axis shows the time of introducing a chip, and the vertical axis shows the corresponding number of transistors included.
Courtesy of Intel Corporation. (B) Shows the number of transistors per DRAM memory chip. Similarly, the horizontal axis shows the time of
introducing a chip, and the vertical axis shows the corresponding number of transistors included.
is being given comparable weight to area and speed considerations
(Najm, 1994). Several important factors have also contributed
to this increased concern about power. One of these
primary driving factors has been the remarkable success and
growth of the personal computing device (e.g., Pass portable
desktops, audio- and video-based multimedia products, etc.)
and wireless communications systems (e.g., personal digital
assistants, personal communicators, etc.) that demand highspeed
computation and complex functionality with low-power
consumption (Pedram, 1995). Unfortunately, this rapid development
in VLSI has not been reflected in developments in
battery technology, and without low-power design techniques,
current and future portable devices will suffer from either very
short battery life or very heavy battery pack (Pedram, 1995;
Najm, 1994; Athas et al., 1994; Landman and Rabaey, 1995;
Tsul et al., 1995; Chang and Pedram, 1997; Bajwa et al., 1997).
It is clear that in the absence of low-power design techniques,
portable and handheld products would suffer from a very
short battery life, and packing and cooling them would be
very difficult (Tsui et al., 1995; Ko et al., 1995). These factors
lead to an unavoidable increase in the cost of the product, as
shown in Figure 5.7. In addition, reliability is strongly affected
266 Tarek Darwish and Magdy Bayoumi
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FIGURE 5.3 Logic Density and Performance Boosting. (A) The
logic density, another measurement for number of transistors per
chip, doubles every new process generation. The trend is clear for
Intel microprocessors. The horizontal axis shows the process generation,
and the vertical axis shows the logic density for microprocessors
manufactured at the corresponding process. Courtesy of Intel Corporation.
(B) This figure shows the frequency trend for VLSI processors.
Almost same trend can be seen for each generation of processors from
companies such as Intel, IBM, and DEC. The left vertical axis shows
the frequency, the right axis shows the gate delay which decreases for
new processes. The gate delay trend is projected through the straight
line curve. Courtesy of Intel Corporation.
by power consumption. Usually, increased power dissipation
implies high temperature operation, which, in turn, may induce
several failure mechanisms in the system (Landman and
Rabaey; 1995; Chang and Pedram, 1997; Bajwa et al., 1997).
5.3 Sources of Power Consumption in CMOS
Two types of power consumption exist for digital CMOS. The
first, the dynamic power component, may be thought of as
useful because it establishes information by charging and discharging
signal lines; the second type, consisting of shortcircuit
and static power components, is waste and comes
from short-circuit and leakage currents that flow directly
from the power supply to ground. Figure 5.8 shows the relative
behavior of these power components with respect to the input
switching activity for an inverter. The following subsections
introduce the different power components and give their parametric
equations. Much of this material can be found in
(Smith, 1997; Rabaey, 1996; Weste and Eshraghian, 1993;
Kang and Leblebici, 1999).
5.3.1 Dynamic Power Dissipation
The dynamic power dissipation is the power required for the
circuit to perform its anticipated tasks. In other words, it is the
power needed for charging and discharging all nodes in a
CMOS circuit. This power is only consumed when the circuit
input signals change. In CMOS circuits, the dyanmic power
dominates the total power dissipation. Such characteristic is
greatly affected by current processes or the deep sub-micron
processes (DSM), for which the ratio of leakage power to
dynamic power is increasing. More details about this issue
are presented in Subsection 5.3.3. Dynamic power dissipation
is illustrated in Figure 5.9 for a simple static CMOS inverter.
When the input signal falls, the PMOS transistor switches on
while the NMOS transistor switches off, creating a path from
the supply voltage to the output capacitance, thus allowing the
output load to charge up to the supply Voltage. On the other
hand, when the input signal rises, the opposite scenario occurs:
the NMOS transistor switches on, and the PMOS transistor
switches off, creating a direct path from the output load to
ground and allowing the output load to discharge.
If CL represents the total capacitance charged per cycle, then
the dynamic power dissipation is as follows: