online convolution code generator in vhdl

[tauseefmd]

module multiplier_block (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10
);

// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10;

wire [31:0] Y [0:9];

assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
assign Y9 = Y[8];
assign Y10 = Y[9];

//Multipliers:

wire signed [31:0]
w1,
w8,
w7,
w32,
w31,
w4,
w11,
w39,
w56,
w49,
w55,
w78,
w79,
w28,
w83,
w176,
w137,
w44,
w98;

assign w1 = X;
assign w8 = w1 << 3;
assign w7 = w8 - w1;
assign w32 = w1 << 5;
assign w31 = w32 - w1;
assign w4 = w1 << 2;
assign w11 = w7 + w4;
assign w39 = w7 + w32;
assign w56 = w7 << 3;
assign w49 = w56 - w7;
assign w55 = w56 - w1;
assign w78 = w39 << 1;
assign w79 = w1 + w78;
assign w28 = w7 << 2;
assign w83 = w55 + w28;
assign w176 = w11 << 4;
assign w137 = w176 - w39;
assign w44 = w11 << 2;
assign w98 = w49 << 1;

assign Y[0] = w78;
assign Y[1] = w55;
assign Y[2] = w78;
assign Y[3] = w137;
assign Y[4] = w83;
assign Y[5] = w31;
assign Y[6] = w44;
assign Y[7] = w56;
assign Y[8] = w79;
assign Y[9] = w98;

endmodule