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6T SRAM Cell
Static random access memory (SRAM) can retain its stored information as long as power is supplied. This is in contrast to dynamic RAM (DRAM) where periodic refreshes are necessary or non-volatile memory where no power needs to be supplied for data retention, as for example flash memory. The term random access'' means that in an array of SRAM cells each cell can be read or written in any order, no matter which cell was last accessed.
The structure of a 6 transistor SRAM cell, storing one bit of information, can be seen in Figure 7.18. The core of the cell is formed by two CMOS inverters, where the output potential of each inverter \ensuremath {V_\textrm {out}} is fed as input into the other \ensuremath {V_\textrm {in}}. This feedback loop stabilizes the inverters to their respective state.
The access transistors and the word and bit lines, WL and BL, are used to read and write from or to the cell. In standby mode the word line is low, turning the access transistors off. In this state the inverters are in complementary state. When the p-channel MOSFET of the left inverter is turned on, the potential \ensuremath{V_\textrm{l,out}} is high and the p-channel MOSFET of inverter two is turned off, \ensuremath{V_\textrm{r,out}} is low.
To write information the data is imposed on the bit line and the inverse data on the inverse bit line, $\overline{\mathrm{BL}}$. Then the access transistors are turned on by setting the word line to high. As the driver of the bit lines is much stronger it can assert the inverter transistors. As soon as the information is stored in the inverters, the access transistors can be turned off and the information in the inverter is preserved.
Static random-access memory
Static random-access memory (static RAM or SRAM) is type of semiconductor memory that uses bistable latching circuitry (flip-flop) to store each bit. SRAM exhibits data remanence,[1] but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered.
The term static differentiates SRAM from DRAM (dynamic random-access memory) which must be periodically refreshed. SRAM is faster and more expensive than DRAM; it is typically used for CPU cache while DRAM is used for a computer's main memory.