encoder and decoder with vhdl implimentation

[udaybiet]

Priority Encoders
Binary Encoders generally have a number of inputs that must be mutually exclusive, i.e. only one of the inputs can be active at any one time. The encoder then produces a binary code on the output pins, which changes in response to the input that has been activated.
Priority Encoding
Because it is always possible when using input switches that more than one input may be active at a single time, most encoders of this type feature priority encoding where, if more than one input is made active at the same time, the output will select only the most significant active input. For example, if 6 and 7 are pressed together the BCD output will indicate 7. The Pinout diagram for the 74HC147 10-to-4-line priority encoder from NXP (Philips Semiconductor), is illustrated in Fig.4.4.1.

Chip Enable Inputs
Some other encoder ICs also feature extra inputs and outputs that allow several ICs to be connected together to achieve more flexibility in the numbers of input and output lines available. These include ENABLE inputs, (typically labelled E), which may consist of one or more input pins that need to have a particular logic level applied (usually logic 0) in order to activate the encoding action. In the absence of a correct ENABLE signal the output pins of the IC will remain in their inactive state.
Switch Bounce
One problem with combinational logic circuits is that unintended changes in output data can occur during the times when the outputs of the IC are changing. This can be due to problems such as switch contacts bouncing as they close, creating rapid and unpredictable changes in logic levels for a very short time, however logic IC operate at high speed and will respond to these very fast changes.
Race Hazards
Problems can also occur due to race hazards where different paths that digital signals take through a logic circuit may have different numbers of gates. For example two logic signals that change simultaneously at two circuit inputs may take different routes through the circuit before being applied to some common gate later in the circuit. However, if one signal passes through six gates for example, while the other signal passes through seven gates, each of the signals will have encountered a different total propagation delay due to the different number of gates they encountered. Therefore they will each arrive at the common gate at slightly different times, and so for a very short time an unexpected logic level may occur at that gate output.
In using combinational logic ICs such as an encoder, problems like switch bounce and race hazards must be allowed for, and one (though not necessarily the best) solution can be to temporarily make the ENABLE pin high during times when data is likely to change. This disables the encoder for a short time until the signal data has settled at its new state, so that there is no chance of errors at the output during changes of input signals.

[rej_bozz]

Digital visual interface transmitter and receiver in
a multimedia system allow for transmitting of high definition
video and audio data between the source and the receiver across
a serial page link at high speeds. This project highlights a detailed
development of digital visual interface (DVI) transmitter and
receiver in multimedia system. These include developing the
architecture DVI receiver and transmitter, high speed
serializer, clock and data recovery circuits and deserializer
through the efficient use of FPGA resources. The project makes
use of TMDS (Transition Minimized Differential Signaling)
technique, that involves advanced TMDS encoding and
decoding algorithms using DC balanced transmission, and helps
reducing EMI over the transmission lines.

The VHDL code for the encoder circuit is brought out
and verified for the values of the tabular column given and
the waveforms are obtained for the same as given in fig. This
TMDS encoder is a programmable logic component that
implements the 8b/10b encoding algorithm required by the
DVI and HDMI video interfaces.The conventional analog video graphics array (VGA)
standard has been replaced by the standard digital visual
interface (DVI) with the evolution of the display technology.
Digital multimedia interface made use of LVDS technology,
in the LVDS technology cable length was limited to short
distance. The proposed work makes use of TMDS technology
with TMDS encoding and decoding algorithms to overcome
the drawbacks of the LVDS technology
The digital visual interface (DVI) specification
provides a high speed digital connection for visual data types
that are display technology independently. The interface is
primarily focused at providing a connection between a
computer and its display device. The DVI transmitter and
receiver are connected through a single or dual TMDS serial
link. The TMDS page link is used to send graphics data to the
monitor. A TMDS page link consists of a single clock channel and
three data channels (RGB). The transitions minimization is
achieved by implementing advanced encoding algorithm on
each of the three channels, convert 8 bit of video or audio
data into a 10 bit transition minimized DC balanced
sequence. This advance coding algorithm enables robust
clock recovery and data recovery at the receiver. Thus, it
achieves greater skew tolerance for transmission over longer
cable length. In the TMDS standard the type of I/O logic,
which is CML (Current Mode Logic circuit), is also included
hence the name TM due to the encoder/decoder and DS
relates to the I/O circuit.

[arunaswetapadma]

Greetings, I am MISHAEL JOSEPHAT, a student at University of Dar es salaam. I am working on a final year project which is about design of Huffman encoder for text data compression by using fpga. I am required to use VHDL to program my fpga. Please help me with the sample design of the system which includes necessary procedures and circuits if possible, I appreciate your efforts in helping the upcoming designers in Telecommunications field.
THANK YOU