08-16-2017, 08:32 PM
1. Introduction
In modern semiconductor devices, the effects of physical lattice strain are playing an increasingly important role. One reason for this is that as device dimensions have shrunk, strains due to lattice mismatch or differences in thermal expansion have become more prevalent. Another is that strain has become an important tool in modifying and enhancing the electrical properties of the semiconductor materials [1]. Large strain induced gains in both electron and hole mobilities have been reported [2][3]. In this article, we will show how SILVACO tools can be used to simulate the creation of a 3D FinFET using VICTORY CELL, calculate the internal strains using VICTORY STRESS, and analyze its electrical characteristics using VICTORY DEVICE.
2. VICTORY CELL
VICTORY CELL was used to generate the FinFET structure based on specifications provided in a mask layout file. VICTORY CELL uses fast, robust and accurate geometrical etch/deposition for Manhattan type structures and fast physical isotropic and anisotropic etch for spacer creation etc. This simulator is perfectly suitable for quick simulation of process parameter variation and design of experiments.
We used VICTORY CELL to build up a FinFET structure with a 50x50 nm fin, 1 m in length. The fin was deposited on a SiO2sub> base layer and a 2 nm gate isolation layer separated it from the 50 nm polysilicon gate crossing it at right angles. A 100 nm Si3N4 capping layer was deposited on top of the structure.