ferroelectric ram seminars report

[ravishankar]

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ABSTRACT
Ferroelectric memory is a new type of semiconductor memory, which exhibit short programming time, low power consumption and nonvolatile memory, making highly suitable for application like contact less smart card, digital cameras which demands many memory write operations.
A ferroelectric memory technology consists of a complementary metal-oxide-semiconductor (CMOS) technology with added layers on top for ferroelectric capacitors. A ferroelectric memory cell has at least one ferroelectric capacitor to store the binary data, and one transistor that provide access to the capacitor or amplify its content for a read operation. Once a cell is accessed for a read operation, its data are presented in the form of an analog signal to a sense amplifier, where they are compared against a reference voltage to determine their logic level.
Ferroelectric memories have borrowed many circuit techniques (such as folded-bitline architecture) from DRAM s due to similarities of their cells and DRAM s maturity. Some architectures are reviewed here.

INTRODUCTION
Before the 1950 s, ferromagnetic cores were the only type of random-access, nonvolatile memories available. A core memory is a regular array of tiny magnetic cores that can be magnetized in one of two opposite directions, making it possible to store binary data in the form of a magnetic field. The success of the core memory was due to a simple architecture that resulted in a relatively dense array of cells. This approach was emulated in the semiconductor memories of today (DRAM s, EEPROM s, and FRAM s). Ferromagnetic cores, however, were too bulky and expensive compared to the smaller, low-power semiconductor memories. In place of ferromagnetic cores ferroelectric memories are a good substitute. The term ferroelectric indicates the similarity, despite the lack of iron in the materials themselves.
Ferroelectric memory exhibit short programming time, low power consumption and nonvolatile memory, making highly suitable for application like contact less smart card, digital cameras which demanding many memory write operations. In other word FRAM has the feature of both RAM and ROM. A ferroelectric memory technology consists of a complementry metal-oxide-semiconductor (CMOS) technology with added layers on top for ferroelectric capacitors. A ferroelectric memory cell has at least one ferroelectric capacitor to store the binary data, and one or two transistors that provide access to the capacitor or amplify its content for a read operation.
A ferroelectric capacitor is different from a regular capacitor in that it substitutes the dielectric with a ferroelectric material (lead zirconate titanate (PZT) is a common material used)-when an electric field is applied and the charges displace from their original position spontaneous polarization occurs and displacement becomes evident in the crystal structure of the material. Importantly, the displacement does not disappear in the absence of the electric field. Moreover, the direction of polarization can be reversed or reoriented by applying an appropriate electric field.
A hysteresis loop for a ferroelectric capacitor displays the total charge on the capacitor as a function of the applied voltage. It behaves similarly to that of a magnetic core, but for the sharp transitions around its coercive points, which implies that even a moderate voltage can disturb the state of the capacitor. One remedy for this would be to modify a ferroelectric memory cell including a transistor in series with the ferroelectric capacitor. Called an access transistor, it wo control the access to the capacitor and eliminate the need for a square like hysteresis loop compensating for the softness of the hysteresis loop characteristics and blocking unwanted disturb signals from neighboring memory cells.
Once a cell is accessed for a read operation, its data are presented in the form of an anal signal to a sense amplifier, where they are compared against a reference voltage to determine the logic level.
Ferroelectric memories have borrowed many circuit techniques (such as folded-bitline architecture) from DRAM s due to similarities of their cells and DRAM s maturity. Some architectures reviewed are,
Wordline-parallel Plateline (WL//PL);
Bitline-parallel Plateline (BL//PL);
Segmented plateline (segmented PQ);
Merged Wordline/Plateline architecture (ML);

BASIC MEMORY CELL STRUCTURE
A ferroelectric memory cell, known as IT- IC (one transistor, one capacitor) ,structure which is similar to that of DRAM. The difference is that ferroelectric film is used as its storage capacitor rather than paraelectric material as in DRAM.

Fig. 1. Ferroelectric IT-IC structure
Figure above shows memory cell structure, consists of a single ferroelectric capacitor that is connected to a Plateline(PL) at one end and, via an access transistor, to a Bitline(BL) at the other end. Raising the wordline (WL) and hence turning ON the access transistor accesses the cell.
As shown in fig 2 ferroelectric memory technology consists of a CMOS technology with added layers on top for ferroelectric capacitors. Therefore, by masking parts of the design that are not using ferroelectric capacitors, CMOS digital and analog circuits can be integrated together with ferroelectric memories, all in the same chip. Ferroelectric capacitors to sit directly on the top of the transistors by means of stacked vias, hence reducing cell area.

Fig. 2. Ferroelectric Capacitor layers on top of conventional CMOS process

FERROELECTRIC CAPACITOR
The basic building block of FRAM is the Ferroelectric capacitor. A ferroelectric capacitor physically distinguished from a regular capacitor by substituting the dielectric with a ferroelectric material. In a regular dielectric, upon the application of an electric field, positive and negative charges will be displaced from their original positions-a concept that is characterized polarization. This polarization, or displacement, will vanish, however, when the electric field return back to zero. In, a ferroelectric material, on the other hand, there is a spontaneous polarization displacement that is inherent to the crystal structure of the material and does not disappear in the absence of electric field. The direction of this polarization can be reversed or reoriented by applying an appropriate electric field.

Fig. 3. Two stable state in a Ferroelectric Material
Widely used dielectric material is Lead Zirconate Titanate (PZT) with formula Pb(Zrx Ti1-x )03. Fig 3 illustrates a unit cell of this material. The central atom in this unit cell either Titanium (Ti) or Zirconium (Zi), depending on the contribution of each atom to the material formula. Lead (Pb) are at the corner of the cube and Oxygen (02) at the face center of the cub lattices.
When the electric field applied to ferroelectric crystal, the central atom moves in the direction of the field. As the atom moves with in the crystal, it passes through an energy barrier causing a charge spike. Although the polarization of each individual unit cell is tiny, the non polarization of several domains-each consisting of a number of aligned unit cells-can be large enough for detection using standard sense amplifier designs. The gross effect of polarization is nonzero charge per unit area of the ferroelectric capacitor that exists at 0 V and does not disappear over time. Which exhibit a hysterisis loop like ferromagnetic material and nonvolatile property.

Fig. 4 Hysteresis loop characteristic of a Ferroelectric Capacitor
A hysteresis loop for a ferroelectric capacitor, as shown in Fig. 4, displays the total charge on the capacitor as a function of the applied voltage. When the voltage across the capacitor is 0 V, the capacitor assumes one of the two stable states: 0 or 1. The total charge stored on the capacitor is Qr. for a 0 or for a 1. A 0 can be switched to a 1 by applying a negative voltage pulse across the capacitor. By doing so, the total charge on the capacitor is reduced by 2Qr, a change of charge that can be sensed by the sense circuitry. Similarly, a 1 can be switched back to a 0 by applying a positive voltage pulse across the capacitor, hence restoring the capacitor charge to +Qr. These characteristics are all very similar to those of a magnetic core except the hysteresis loop of a ferroelectric capacitor does not have sharp transitions around its coercive points:-Vc, and +Vc. This reflects a partial switching of electric domains in a ferroelectric capacitor, and further implies the even a voltage half of Vmax , can disturb the state of the capacitor. As a result, it is impossible access a ferroelectric capacitor in a cross-point array without disturbing the capacitors on the same row or column.
As a remedy this situation would be to modify the ferroelectric material processing in order to create a square-like hysteresis loop. As magnetic core form a core memory. This is a technical development that we may expect in near future.
Another approach is to modify a ferroelectric memory cell by including a transistor in series with the ferroelectric capacitor. The transistor, called the access transistor, controls the access to the capacitor and eliminates the need for square-like hysteresis loop. When the access transistor is OFF, the FE capacitor remains disconnected from bitline (BL) and hence cannot be disturbed. When the access transistor is ON, the FE capacitor is connected to the bitline and can be written to or read by the plateline (PL). In other words, the presence of an access transistor in series with the ferroelectric capacitor compensates for the softness of its hysteresis loop characteristics and block unwanted disturb signals from neighbouring memory cells.
BASIC MEMORY CELL OPERATION
The principles of operation of ferroelectric capacitor and ferromagnetic core are similar. We first discuss the principle of operation of ferromagnetic memories, which make it easier to understand the operation of ferro electric cell.
FERROMAGNETIC CORE
A core memory, as shown in Fig. 5, consists of a regular array of tiny .magnetic cores that can be magnetized in one of two opposite directions, hence storing binary data in the form of a magnetic field. A write access into a core consists of sending simultaneous current pulses through the core via its x-access and y-access wires. Depending on the directions of the current pulses, a core is magnetized in a 0 or a 1 direction. The basic assumption here is that only the core that receives two simultaneous current pulses is affected. All the remaining cores, including those that receive one current pulse or none, retain their original magnetization.

Fig. 5. Two-dimension array of Ferroelectric
A read access Consists of a write access followed by sensing. We write a 0 to the core is order to discover the original data content of the core. If the original content of the core is a 1, writing a 0 would mean changing the magnetic direction of the core. This induces a large current spike on the sense wire. On the other hand, there will be no current spike on the sensing wire if the original content of the core was also a 0. Therefore, by sensing the presence of a current spike or the sensing wire, the original data of the accessed core are determined.
The read operation as explained above is destructive since a 0 is written to any core that is accessed for a read. The original data, however, are saved at the sense amplifier and can be restored back into the accessed core. In other words, a read access is only complete after the second write that restores the original data.
FRAM WRITE OPERATION
The cell consists of a single ferroelectric capacitor that is connected to a PL at one end and via an access transistor, to a BL at the other end. The cell is accessed by raising the wordline (WL) and hence turning ON the access transistor. The access is one of two types: a write access or a read access.
The timing diagram for a write operation is shown in Fig.6. To write a 1 into the memory cell, the BL is raised to VDD. Then the WL is raised to VDD + Vr (known as boosted VDD) where VT is the threshold voltage of the access transistor. This allows a full VDD to appear across the ferroelectric capacitor (-VDD) according to the voltage convention adopted in Figure). At this time, the state of the ferroelectric capacitor is independent of the initial state of the FE capacitor, as shown in Figure. At this time the state of ferroelectric is independent of its initial state. Next, the PL is pulsed, that is, pulled UP to VDD and subsequently pulled back down to ground. Note that the WL stays activated until the PL is

Fig. 6. Timing diagram for a write operation of the Memory Cell
pulled down completely and the BL is driven back to zero. The final state of the capacitor is a negative charge state S1. Finally, deactivating the WL leaves this stare undisturbed until the next access.
To write a 0 into the cell, the BL is driven to 0V prior to activating the WL. The rest of the operation is similar to that of writing a 1 as shown in Fig. 6.
The written data is held in the cell even though the selection of the wordline is changed to non selected state (i.e. transistor is OFF), so it is nonvolatile. The level of polarization that correspond to the data remain as the state of remnant polarization after the applied voltage is removed.
FRAM READ OPERATION
Similar to ferromagnetic capacitor, read operation is destructive. The original data, however, are saved at sense amplifier and can be restored back. In another word a read access is. Only complete after the second write that restores the original data. -.

Fig. 7. Timing diagram of Read Operation of the Memory Cell
The timing diagram for a read access is shown in Fig. 7. A read access begins by precharging the BL to 0V, followed by activating the WL (to). This establishes a capacitor divider consisting of CFE and CBL between the PL and the ground. Where CBL represent the total amount of parasitic capacitance of the bit line. Depending on the data stored, the capacitance of the FE capacitor can be: approximated by Co or C1. That is CBL and C0 or C1 act as a voltage divider, therefore the voltage developed on the bitline (Vx) can be one of the two. .

At this point, the sense amplifier is activated to drive the BL t VDD if the voltage developed on the BL is V1 or to 0V if the voltage on the BL is Vo. The WL is kept activated until the sensed voltage on the BL restores the original data back into the memory cell and the BL is precharged back to 0V. The sense amplifier can discriminate between a 0 and 1 voltage signal on the BL. This is only possible if a reference voltage, midway between a 0 and a 1 signal.

SENSING SCHEMES
The read access as presented above is known as the step-sensing approach, since a step voltage (the rising edge of a pulse) is applied to the PL prior to sensing. An alternative is the pulse-sensing approach in which a full pulse is applied to the PL prior to activating the sense amplifiers (refer to Fig.8). The charge transferred to the BL in a pulse sensing scheme is either zero for a stored 0 or 2QT for a stored I. Equivalently the voltage developed on the BL is either 0V for a stored 0 or V1 -Vo for a stored 1.
In both step- and pulse-sensing schemes, the voltage difference on the BL that is developed by a stored 1 and a stored 0 is equal to V1 V0. The common-mode voltage, however, is equal to (V1 + Vo)/2 in the step-sensing approach, as compared to (V1 - Vo)/2 in the pulse-sensing approach. Therefore, the step-sensing approach provides a higher common-mode voltage on the BL that simplifies the sense amplifier design when a bias voltage is required. Another advantage of the step-sensing approach is that it provides a faster read access, as the sensing does not wait for the PL to be pulled low.
Both step- and pulse-sensing approaches restore 1, but only the step-sensing approach fully reinforces a 0. To substantiate this point, note that during a read operation in a step-sensing approach, an FE capacitor storing a 0 experiences a voltage sequence Of 0V, VDD V0 VDD and 0V (a full-VDD excursion). In a pulse-sensing approach, the corresponding voltage sequence is 0V, VDD - Vo, and 0 V (aVDD - Vo excursion). None of the two voltage sequences upsets the

Fig. 8. Timing Diagram for Read operation based on step-sensing scheme and
pulse sensing scheme
original data (i.e. 0) of the FE capacitor. However, the latter provides a weak reinforcement of 0 by applying a voltage less than VDD across the capacitor. This seems to deteriorate the capacitor s long-term retention performance. To remedy this situation, a second pulse must be applied to the PL to fully restore the 0 into the capacitor. This implies that the cycle time for the pulse-sensing approach can be twice as large as that of the step-sensing approach.
The pulse-sensing approach applies both the leading edge and the trailing edge of the voltage pulse to the FE capacitor prior to sensing. The trailing edge eliminates the non switching part of polarization that was introduced on the BL by the rising edge and therefore bypasses the effect of non switching part of polarization and its process variations altogether. This seems to be the only advantage of the pulse sensing approach over the step-sensing approach.
FERROELECTRIC MEMORY ARCHITECTURE
Ferroelectric memories have borrowed many circuit techniques from DRAM s due to similarities of their cells and DRAM s mature architecture. A folded-bitline architecture, for example, that was first introduced to replace an older open-bitline architecture in DRAM is now well adopted in FRAM. The bitlines are folded to lie on the same side of a sense amplifier, as shown in Fig. 9, instead of lying open on opposite sides of the sense amplifier, to reduce chances of any bitline mismatch that


Fig. 9. Block diagram of ferroelectric Memory with
(a) an open bitline architecture and
(b) a fold bitline architecture
could occur due to process variations. On the other hand, the requirement for pulsing the plateline in an FRAM has called for original circuit techniques that were not required in a DRAM. There are various memory architectures that have been developed for an FRAM with moving plateline. We discuss these architectures in Section A to D.
A. WORDLINE-PARALLEL PLATELINE (WL//PL)
Fig. 10. shows a simplified block diagram of a WL/ /PL architecture. As its name suggests, the PL is run parallel to the WL in this architecture. When a WL and PL pair is activated, an entire row that shares the same WL and PL is accessed at once. It is impossible, in this architecture, to access a single cell without accessing an entire row. This is in fact common in almost every RAM since the adjacent cells in a row store the adjacent bits of a byte, which are accessed simultaneously. Sometimes, the PL in this architecture is shared between two adjacent rows to reduce the array area by eliminating a metal line. In this case, the unaccessed cells connected to an activated PL can be disturbed. This is due to the voltage that develops across the FE capacitors of the non selected cells with the active PL. Ideally. This voltage to be zero because the storage nodes of the cells should be floating. However, the parasitic capacitance of a storage node forms a capacitor divider with the FE capacitor itself and produces a nonzero voltage across the FE capacitor. For a stored 0 . data, the disturb voltage is in the direction that reinforces the 0. For a stored 1 data, however, the disturb voltage is in the direction of flipping the data. If this voltage is small enough (much less than the coercive voltage of the FE capacitor), it can be ignored. Otherwise, a data 1 can be flipped by a sequence of small voltage disturbances.

Fig. 10. Block Diagram of Ferroelectric Memory with WL//PL architecture
B. BITLINE-PARALLEL PLATELINE (BL//PL)
Fig. 11. shows an array architecture in which the PL is run parallel to the BL, hence the name BL//PL for the architecture. Unlike the previous architecture, only a single memory cell can be selected by a simultaneous activation of a WL and a PL. This is the memory cell that is located at the
Intersection of the WL and the PL. It is possible to select more than one memory cell in a row by activating their corresponding platelines.
This architecture absorbs the function of a y-decoder in the selection of the platelines. File activation of the sense an is controlled by the same signal as the PL. Therefore, only one sense amplifier is activated if only one memory cell needs to be accessed. This reduces the power consumption significantly.

Fig.11. Block Diagram of Ferroelectric Memory with BL//PL architecture
On the other hand, if an entire row needs to be accessed, then all the platelines are selected simultaneously, hence increasing the dynamic power consumption due to charging and discharging the platelines.
The main disadvantage of this architecture is that activating a PL could disturb all the cells in the corresponding column. This is very similar to the situation discussed for the WL//PL architecture with PL shared between two adjacent rows.
C. SEGMENTED PLATELINE (SEGMENTED PL)
WL//PL architecture is power consuming and relatively slow because the PL is activated in its full length to access all the cells in the row at once. Also, a BL//PL architecture could be power consuming if multiple platelines are activated to access multiple memory cells in the selected row.

Fig. 12. Block Diag, of Ferroelectric Memory with Segmented-PL archilecture
For larger arrays, the PL can be segmented into local platelines (LPL s) that run parallel to the WL and controlled by a global plateline (GPL) that runs parallel to the BL. As shown in Fig. 12. a GPL is ANDed with the WL to generate the signal for the LPL. Since the LPL is only connected to a few memory cells (eight in this example), it can respond much faster than a PL in the WL//PL architecture Also, since the WL gates the GPL, there is no disturbance to the non selected cells in the column, as it was in the BL//PL architecture.
Among the three architectures discussed so far, the segmented-PL architecture seems to be the most feasible architecture for a large-density ferroelectric memory. A compromise between speed and power consumption can be made by choosing the number of LPL s per GPL.
D. MERGED WORDLINE//PLATELINE (ML) ARCHITECTURE
A WL and its neighboring PL in WL//PL architecture can be merged to form a single merged line (ML) in this architecture. Fig. 13. shows the circuit diagram of two IT-IC memory cells or a single 2T-2C cell connected to two ML s (ML1 and ML2) and two bitlines (BLn and BLn+l).

Fig. 13. Circuit Diagram of a pair of Ferroelectric Memory Cells for a Merged-line architecture
Compared to a WL//PL architecture, the ML architecture enjoys a shorter read access time, as the PL capacitance is-now divided equally between two merged lines. This allows the merged line to respond twice as fast, assuming that the original wordline capacitance is negligible compared to the original plateline capacitance. The read/write cycle time, however, remains the same in both architectures. This is due to the fact that four transitions are required for a full read/write operation, instead of two in WL//PL architecture. Finally, the ML architecture can achieve higher density compared to the WL//IPL architecture due to reduced number of access wires, that is, using a single merged line instead of a wordline and a plateline. This higher density comes at the expense of complicated processing steps such as stacking the bottom electrode of the FE capacitor right on top of the transistor gate and providing a side contact (plug) to the top electrode from the transistor source/drain area.
COMPARISON
The memory cell of FRAM is configured with one transistor and one capacitor is DRAM. It can also hold data even when the power is switched off as can flash memory, which is a representative nonvolatile memory device. FRAM has a well-balanced combination of features of both RAM and ROM.
FRAM can be rewritten more than 108 times, which is comparable to DRAM or SRAM in actual applications, while flash memory can be written to 105 times at maximum.
FRAM dose not need an erase operation before it is rewritten. This is similar to DRAM or SRAM. On the other hand, Flash memory (or specific sectors) must he erased once to he rewritten. FRAM is characteristically easy to operate because it does not need to he refreshed to hold data unlike DRAM.

CONCLUSION
Looking toward the future, we-anticipate progress in three areas: density, access and cycle times, and use as an embedded memory in system-on-chip technology. The density of commercial ferroelectric memory has improved dramatically over the past three years from 64 to 256 kb, with I-Mb densities expected soon.
Ferroelectric memories, on the other hand, are superior to EPROM s and Flash memories in terms of write-access time and overall power consumption, and hence, target applications where a nonvolatile memory is required with such features. Two examples of such applications are Contactless smart cards and digital cameras. Contactless smart cards require nonvolatile memories with low power consumption, as they use only electromagnetic coupling to power up the electronic chips on the card. Digital cameras require both low power consumption and fast frequent writes in order to store and restore an entire image into the memory in less than 0.1s.
Another advantage of ferroelectric memories over EEPROM s and Flash memories is that they can be easily embedded as part of a larger integrated circuit to provide system-on-a-chip solutions to various applications. Future personal wireless connectivity applications that are battery driven, such as third-generation cellular phones and personal digital assistants, will demand large amounts (multiple megabytes) of nonvolatile storage to retain accessed Internet Web pages, containing compressed video; voice, and data. The density and energy efficiency of writing data to memory would seem to indicate that ferroelectric memory will play a major role in these types of consumer products.

REFERENCES
1. PROCEEDINGS OF THE IEE, May 2000
2. WW.RAMTRON.COM
3. WW.FUJITSU


CONTENTS
INTRODUCTION 1
BASIC MEMORY CELL STRUCTURE 3
FERRO CAPACITOR .. 5
BASIC MEMORY CELL OPERATION . 8
FERROMAGNETIC CORE . 8
FRAM WRITE OPERATION ..10
FRAM READ OPERATION 11
SENSING SCHEME: 14
FERROELECTRIC MEMORY ARCHITECTURE 16
A.WORDLINE-PARALLEL PLATE LINE .. 17
B. BITLINE-PARALLEL PLATELINE (BL//PL) ..18
C. SEGMENTED PLATELINE (SEGMENTED PL) . .19
D. MERGED WORDLINE//FLATELINE (ML) ..21
COMPARISON .22
CONCLUSION ..23
REFERENCE ..24

ACKNOWLEDGEMENT
I extend my sincere thanks to Prof. P.V.Abdul Hameed, Head of the Department for providing me with the guidance and facilities for the Seminar.
I express my sincere gratitude to Seminar coordinator
Mr. Berly C.J, Staff in charge, for their cooperation and guidance for preparing and presenting this seminars.
I also extend my sincere thanks to all other faculty members of Electronics and Communication Department and my friends for their support and encouragement.
HASHIM MOHAMMED

[abhilashkp]

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ABSTRACT

FRAM is a type of non-volatile read/write random access semiconductor memory. FRAM combines the advantages of SRAM writing is roughly as fast as reading, and EPROM non-volatility and in-circuit programmability. FRAM (ferroelectric RAM) is a random access memory that combines the fast read and write access of dynamic RAM (DRAM) - the most common kind of personal computer memory - with the ability to retain data when power is turned off (as do other non-volatile memory devices such as ROM and flash memory). Because FRAM is not as dense (can not store as much ata in the same space) as DRAM and SRAM, it is not likely replace these technologies. It is fast memory with a very low power requirement, it is expected to have many applications in small consumer devices such as personal digital assistants (PDA), handheld phones, power meters, and smart card, and in security systems. FRAM is faster than flash memory. It is also expected to replace EEPROM and SRAM for some applications and to become a key component in future wireless products.

INTRODUCTION:
A ferroelectric memory cell consists of a ferroelectric capacitor and a MOS transistor. Its construction is similar to the storage cell of a DRAM. The difference is in the dielectric properties of the material between the capacitor's electrodes. This material has a high dielectric constant and can be polarized by an electric field. The polarisation remains until it gets reversed by an opposite electrical field. This makes the memory non-volatile. Note that ferroelectric material, despite its name, does not necessarily contain iron. The most well-known ferroelectric substance is BaTiO3.
A Ferroelectric memory cell consists of a ferroelectric capacitor and a MOS transistor. Its construction is similar to the storage cell of a DRAM. The difference is in the dielectric properties of the material between the capacitor's electrodes. This material has a high dielectric constant and can be polarized by an electric field. The polarisation remains until it gets reversed by an opposite electrical field. This makes the memory non-volatile.
Data is read by applying an electric field to the capacitor. If this switches the cell into the opposite state (flipping over the electrical dipoles in the ferroelectric material) then more charge is moved than if the cell was not flipped. This can be detected and amplified by sense amplifiers. Reading destroys the contents of a cell which must therefore be written back after a read. This is similar to the precharge operation in DRAM, though it only needs to be done after a read rather than periodically as with DRAM refresh.
FRAM is found mainly in consumer devices and because of its low power requirements, could also be used in devices that only need to activate for brief periods. FRAM allows systems to retain information even when power is lost, without resorting to batteries, EEPROM, or flash. Access times are the same as for standard SRAM, so there's no delay-at-write access as there is for EEPROM or flash. In addition, the number of write cycles supported by the FRAM components is nearly unlimited up to 10 billion read/writes. FRAM combines the advantages of SRAM - writing is roughly as fast as reading, and EPROM - non-volatility and in-circuit programmability

FRAM Technology
When an electric field is applied to a ferroelectric crystal, the central atom moves in the direction of the field. As the atom moves within the crystal, it passes through an energy barrier, causing a charge spike. Internal circuits sense the charge spike and set the memory. If the electric field is removed from the crystal, the central atom stays in position, preserving the state of the memory. Therefore, the FRAM memory needs no periodic refresh and when power fails FRAM memory retains its data. It's fast, and doesn't wear out!
To increase the memory capacity, the cell size must always be reduced, and the design, process, and materials have been improved aggressively for this purpose. ferroelectric RAM products (FRAMs) are the most advanced of the flash challengers. The pioneer, Ramtron International Corp. (Colorado Springs, Colo.), has been selling FRAM chips since 1992. Their memory capacities are low, however, the largest being 256Kb still a small fraction of the multimegabit chips offered by the major flash memory makers. In current commercial FRAMs, the interconnects that page link individual transistors into circuits are 0.5 m wide and operate at 3 V. Narrower interconnects are desirable so that memory cells may be made smaller and be packed in greater numbers onto an IC. Ramtron's FRAMs are made by Fujitsu Ltd., Tokyo, which also sells its own FRAM products, mostly as embedded memory in microcontrollers and smart cards.
The biggest hurdle for FRAM developers is to advance the manufacturing technology to smaller geometries and lower voltages. R&D at Ramtron is aiming at 0.35- m interconnect widths and 1.8-V operation. And last November, Texas Instruments Inc. (Dallas) announced that it had built a 64Mb FRAM in a standard 0.13- m CMOS process, using technology licensed from Ramtron.
At the core of an FRAM cell is a capacitor filled with a ferroelectric crystalline material, usually a lead-zirconium-titanate (PZT) compound .Each unit cell (a crystal's basic building block) of a ferroelectric material has a permanent electric field around it. That's because the geometric center of all the electrons in the unit cell is at a different spot from the geometric center of all the protons. It's as though two small particles with equal and opposite charges are separated from each other by a short distance in short, it is an electric dipole.
Many materials form electric dipoles. But what sets ferroelectric materials apart from other dipolar materials is that millions of dipoles, in a region called a domain, line up to point in the same direction. When an electric field is applied in the opposite direction, the dipoles flip over so that they again point in the direction of the electric field.
Each unit cell of PZT is shaped like an elongated cube. At each of the cube's eight corners is an atom of lead; in the center of each cube face is an oxygen atom; and in the interior of the cube is an atom of either zirconium or titanium. This last has two stable positions, explains Mike Alwais, Ramtron's vice president of FRAM products: "One is near the cube's top face and the other is near the bottom."
Apply an electric field and the atoms in the interiors of all the unit cells in the ferroelectric material move in the field's direction. Remove the field and the atoms stay put. The positions of the atoms in the cubes store the bit of data, a binary 1 or 0.
To read a bit, an electric field is applied. If the atoms are near the cube "floors" and the electric field pushes them to the top, the cell gives off a current pulse. This pulse, representing a stored 1 or 0, is detected by a sense amplifier. Contributing to pulse amplitude are the movements of the interior atoms in the crystals of the ferroelectric material and the capacitor itself. If the atoms are already near their cubes' "ceilings," they don't budge when the field is applied and the cell gives off a smaller pulse, due only to the electric charges stored on the cell capacitor.
Reading an FRAM cell destroys the data stored in its capacitor. So after the bit is read, the sense amplifier writes the data back into the cell, just as in a DRAM.
The FRAM in fact is like the DRAM in every way but one: the DRAM cell's capacitor is of a nonferroelectric material, usually silicon dioxide. When data is stored as charge on the DRAM cell's capacitor, the charge leaks away into the silicon substrate almost immediately unless it is rewritten several times a second. That requirement drives up power consumption, and of course when the power is turned off, the charge stored in the capacitors quickly disappears.
Because the basic operation and structure of the FRAM and the DRAM are so similar, Alwais expects that FRAMs will eventually run as fast as DRAMs with the same memory capacity and cell size. Texas Instruments is interested in FRAMs for embedded applications for example, for on-chip storage of the operating instructions for digital signal processors and microcontrollers.
Memory Basic
FRAM offers a unique set of features relative to other memory technologies. Traditional mainstream semiconductor memories can be divided into two primary categories -- volatile and nonvolatile. Volatile memories include SRAM (static random access memory) and DRAM (dynamic random access memory). They share the property that they lose their contents after power is removed from the electronic system. RAM type devices are very easy to use, and are high performing, but they share the annoying quirk of losing their mind when the lights go out.
Nonvolatile memories do not lose their contents when power is removed. However all of the mainstream nonvolatile memories share a common ancestry that derives from ROM (read only memory) technology. The disadvantage is that read only memory is not easy to write it's impossible. All of its descendants make it very difficult to write new information into them. They include technologies called EPROM (almost obsolete now), EEPROM, and Flash. ROM based technologies are very slow to write.Another disadvantage is that ROM based memories wear out after being written a small number of times, and use a large amounts of power to write.

FRAM offers features consistent with a RAM technology, but is nonvolatile like a ROM technology. FRAM bridges the gap between the two categories and creates something completely new -- a nonvolatile RAM.
FRAM SPECIFATION :
4MB FRAM Nonvolatile Memory Module
Features:
Organization:4 banks >< 32k >< 32 bits
Highest density: Ferroelectric Memory over 22.4kb/mm
10 year data retension at 85o C
Unlimited read /write cycles.
Advanced high reliability ferroelectric process
SRAM & DRAM Compatible
70ns Access time
130ns Cycle time.
Equal access & cycle time for Read and Writes.
LOW POWER OPERATION:
2.7V to 3.6V operation .
15mA Active Current.
15microA stand by Current.
The latest 32-Mbit ferroelectric RAM highest density RAM reported has been developed by Toshiba Corp. This FRAM uses a new chain cell structure that links together eight memory cells .Each cell has a ferroelectric capacitor and field effect transistor in parallel and not in series.The 32Mbit FRAM is made on0.2micron processing ,which provides 1.875square micron cell size on a 96 square millimetre die.

APPLICATIONS:
FRAM is faster than flash memory,because it is fast memory with a very low power requirement, it is expected to have many applications in small consumer devices such as personal digital assistants (PDAs), handheld phones, power meters, and smart card, and in security systems.
A smart card is a plastic card about the size of a credit card, with an embedded microchip that can be loaded with data, used for telephone calling, electronic cash payments, and other applications, and then periodically refreshed for additional use. . A Smart Card is an IC card that contains a microcomputer, storage circuit, and RF circuit. The ferroelectric RAM (FRAM) has been developed as a nonvolatile memory that satisfies the above requirements. An FRAM embedded in an LSI must operate as a low-voltage peripheral logic IC. We have developed a new FRAM sensing scheme that can read bit-line potentials close to the GND potential.
Currently or soon, you may be able to use a smart card to:
Dial a connection on a mobile telephone and be charged on a per-call basis
Establish your identity when logging on to an Internet access provider or to an online bank
Pay for parking at parking meters or to get on subways, trains, or buses
Give hospitals or doctors personal data without filling out a form
Make small purchases at electronic stores on the Web (a kind of cybercash)
Buy gasoline at a gasoline station
Fujitsu has developed Smart Cards and other high-security devices that use secure ferroelectric RAM (FRAM) memory. This type of memory has an anti-tampering function and is used to keep the keys and parameters needed for encryption/decryption algorithms, modify the keys and parameters for application services, store a high-speed calculation table for encryption/decryption systems, and support a firewall between applications.
Contactless Smart Cards in particular have rapidly come into wide use because they are easy to use, can perform high-speed processing, and can be used in a wide variety of applications. In keeping with this trend, Fujitsu has produced various FRAM-embedded (ferroelectric-RAM-embedded) LSIs for Contactless Smart Cards.
Current applications for FRAM memory products can be divided into the following four categories:
Data collection and logging
configuration storage
nonvolatile buffer
SRAM replacement & Expansion
Data Collection & Logging
FRAM allows system designers to write data to nonvolatile memory faster and more often -- a luxury not afforded to users of EEPROMs.
Data collection consists of the acquisition and storage of data, which must be retained in the absence of power (not temporary or scratchpad in nature). These are systems, or subsystems that have the primary function of collecting data that varies over time. In most cases, a history of the changes is important.
End system applications: metering (electric, gas, water, flow), RF/ID, instrumentation, and certain automotive application such as airbag controllers.
Configuration Storage
FRAM helps system designers overcome the woes of sudden power loss by providing the flexibility to store configuration information in real time -- not just on power down.
Configuration storage deals with the tracking of a system as it changes over time. The goal is either to restore its state on power up, or to identify the cause of an error. In general, data collection is often the function of a system or subsystem, where as configuration storage is a low level engineering function regardless of the system type.
End system applications: laser printers and copiers, industrial process control, networking, cable modems and set top boxes, and white goods
Nonvolatile Buffer
FRAM can store operating data quickly, before transmitting or storing in other nonvolatile media.
In this case, information is being sent from one subsystem to another, this information is critical and should not be lost if power fails. In some cases, the target system is a larger storage device. FRAM, with its fast write and high endurance allows the user to store data before it is sent on to another system.
End system applications: industrial systems and in banking systems such as ATM machines, future applications will include hard disk drives with nonvolatile caching.
SRAM Replacement & Expansion
FRAM's fast write and nonvolatile features allow system designers to combine SRAM and EEPROM into one device, or simply expand SRAM.
In many cases, a system uses multiple memory types. FRAM offers the ability to perform ROM, RAM, and EEPROM functions with one device, saving space, power and sometimes cost. The most common example is an embedded microcontroller with external serial EEPROM. FRAM can replace the EEPROM, and offer additional SRAM functionality to the micro as well.
End system applications: all-in-one memories tend to occur in portable applications, and in any system using low-end (resource poor) microcontrollers.
FUTURE APPLICATIONS:
APPLICATIONS OF FRAM ON AUTOMOTIVE APPLICATIONS:-
Today's passenger automobiles and trucks offer increased electronic content and this trend is expected to accelerate. With some 55 million passenger vehicles sold worldwide in 2002 and numerous applications that can benefit from FRAM technology, the automotive market is certainly very attractive for FRAM. The average low end auto has five to ten electronic control units while a luxury car may have fifty to sixty. Recent introductions include improved ABS systems with traction control, continuously variable transmissions, electronic shift, dynamic stability control, and digital radio platforms. In the coming years, new electronic applications will include adaptive cruise control with collision avoidance, DVD players with car navigation, and control by wire (x-by-wire), and crash recording (black-box) technology. Additional sophisticated network technologies will continue to improve behind the scenes automation and performance.
The challenge of handling and storing data is a pervasive theme in the proliferation of automotive electronics. One implication is that increased data handling results in an increase in the frequency of data updates. Existing memory choices are often inadequate in managing the frequent updates. FRAM, with fast write and effectively unlimited endurance offers unique benefits for data handling and storage intensive applications. Consequently it is expected to be widely adopted in automotive applications in the coming years.
The real opportunities for FRAM:
Below are some of the applications for which automotive development engineers are evaluating or designing with FRAM products today.
Airbag
A principle feature of airbag and restraint systems in the near future will be crash recorders, commonly know as black-boxes. The automotive black box will be integrated into the airbag or restraint system, it is unlikely to be a separate assembly such as the aircraft black box. This architecture is attractive because the sensor data that is critical for a crash recorder is largely available to the controller or can be accessed via busses already in place such as CAN.
A crash recorder is a data logger. It may be called on to collect data frequently over a long period of time in a circular buffer, or to respond very quickly based on sensor readings. Ideally the crash recorder would offer both capabilities. In this rugged environment the data must be stored in a true nonvolatile memory as any form of battery backup will present crash survivability challenges. Technologies such as Flash face performance problems as they provide write endurance which is limited when it comes to long term data collection and they are far too slow to store data in the moment of impact. Crash statistics show high percentages of serious crashes result in a power outage during the crash, therefore data must be stored instantly and in a non-volatile state, before power leaves the vehicle and data is lost. Ramtron is a member of the IEE P1616 committee to define a standard for Motor Vehicle Event Data Recorders (MEVDR). As a result we have gained valuable insight into data recorder requirements. Today crash recorders are being designed with FRAM products from 16Kb to 64Kb, typically with a SPI interface such as the FM25640.
Telematics/navigation
Telematic functions are increasingly part of a high end vehicle electronics package. These systems provide dynamic maps that allow routing to be adjusted based on traffic patterns or other criteria. FRAM memories are used today in such system to store navigation waypoints, bookmarks etc. 16Kb memories are commonly used in this application. Last year Matsushita selected Ramtron's FRAM for its in-car navigation system. The 16K FM25C160 s fast read/write and high-endurance features provide Matsushita mobile automotive devices with a distinctive resume play function. The FM25C160 stores scene changes and unique user data upon power down, enabling the user to continue where they left off when the unit is powered back up.
Entertainment
Digital car radios are gaining in popularity. Such radios can download station information and store it in nonvolatile memory. The uncertainty of changes in this data makes it risky to use a limited endurance memory such as EEPROM. A common work-around is to maintain such download data in RAM and write it when power is turned off. This requires the use of a large capacitor which can maintain power on the EEPROM while it is written. While inexpensive, these capacitors are physically bulky and undesirable in ever shrinking electronic radios. Matsushita designed a 16K FRAM into their in-car entertainment systems. The FM25C160 saves system board space by eliminating components and allowing a reduced capacitor size, which would not be possible with alternative memory solutions.
Instrument Cluster
Instrument clusters provide varying capabilities. The presence of a low density nonvolatile memory is common, and tracking elapsed miles often leads to frequent writes. The problem of intermittent data errors is frequently experienced by users in this application, possibly associated with electrical noise interfering with slower writing nonvolatile memories. A 4Kb FRAM such as the FM24C04 has been used in such instrumentation with great success and provides robust operating and data integrity in a noisy environment.
Tire Pressure
Automobiles are adopting tire pressure sensing technology in order to mitigate the risks associated with driving with under-inflated tires. Today this technology is implemented by sensing rotational differences between tires and inferring tire pressure. Future systems will likely involve direct sensor technology that can measure tire pressure. A natural extension of this data generation is logging. A historical record of tire pressures could present compelling documentation in determining liability should tire pressure contribute to an accident. Tire pressure logs might be implemented in the car and also in the tire, and FRAM is an ideal solution for this application given its unlimited ability to write in low power environments, such as that of a tire-based historical logger.
ABS - Stability Control
ABS has evolved from its basic form to include traction control and more recently to include stability control. Traction control uses the wheel slip information already produced by ABS sensors to regulate power to prevent spinning tires due to slippery conditions. Stability control is a more sophisticated variety where power is regulated to each wheel depending on driving conditions. Based on speed, turn radius and road conditions the rotation of individual wheels is managed. Such systems are very sophisticated and involve learning algorithms. To use a FRAM for example in this application would be more suitable for users since FRAM allows for unrestricted updates of system data. Currently temperatures for FRAM are specified to 85C and ABS system electronics must normally operate at 125C, however the road map for FRAM products includes meeting these temperature requirements.
Power Train
Like stability control, power train management systems are ever more adaptive and can benefit from a nonvolatile memory that can be updated quickly and often. Also like ABS, these systems operate at 125C and will depend on a future generation of FRAM products, most likely 256Kb parts rated at 125C or higher.

ADVANTAGES:
1. FRAM allows systems to retain information even when power is lost, without resorting to batteries, EEPROM, or flash.
2. Access times are the same as for standard SRAM, so there's no delay-at-write access as there is for EEPROM or flash.
3. Low power consumption , low voltage operation and high write endurance make it superior than other non-volatile memories like EEPROM & FLASH
4. It is less expensive than magnetic memories which require 4 extra mask
DISADVANTAGE:
1. Present high cost .
2. Low density compared to DRAM & SRAM.
FUTURE OF FRAM:
Development of FRAM in full range of densities and operating temperatures to support automotive data handling and storage applications will find a wide variety of applications as said above.
In addition, the FRAM technology can easily be combined with logic and mixed signal technologies to offer more cost effective integrated solutions in the future.
CONCLUSION
The biggest obstacle to large memories is their large power consumption, particularly for wireless applications. But FRAM s advantage is the low power consumption compared to other new memory technologies , and hence economic. The wide range of applications it has in case of SMART cards and data storage applications, together with the future automotive applications make it one of the best memories among the new memory technologies among ferromagnetic and ovonic memories.

REFERENCES
Information Technology Magazine
http://iee.org
http://eetuk.com
http://savemyfiles.com


CONTENTS
INTRODUCTION
FRAM TECHNOLOGY
MEMORY BASICS
ADVANTAGES & DISADVANTAGES.
APPLICATIONS OF FRAM.
(a)CURRENT APPLICATIONS
(b)FUTURE APPLICATIONS
CONCLUSION

ACKNOWLEDGMENT

I express my sincere thanks to Prof. M.N Agnisarman Namboothiri (Head of the Department, Computer Science and Engineering, MESCE), Mr. Sminesh (Staff incharge) for their kind
co-operation for presenting the seminars.
I also extend my sincere thanks to all other members of the faculty of Computer Science and Engineering Department and my friends for their co-operation and encouragement.
ANUSHA.R.C

[abhiz]

Ferroelectric RAM (FeRAM or FRAM is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility. FeRAM is one of a growing number of alternative non-volatile memory technologies that offer the same functionality as Flash memory. FeRAM advantages over Flash include: lower power usage, faster write performance and a much greater maximum number (exceeding 1016 for 3.3 V devices) of write-erase cycles. FeRAM disadvantages are: much lower storage densities than Flash devices, storage capacity limitations and higher cost.Development of FeRAM began in the late 1980s. Work was done in 1991 at NASA's Jet Propulsion Laboratory on improving methods of read out, including a novel method of non-destructive readout using pulses of UV radiation.[2] Much of the current FeRAM technology was developed by Ramtron, a fabless semiconductor company. One major licensee is Fujitsu, who operate what is probably the largest semiconductor foundry production line with FeRAM capability. Since 1999 they have been using this line to produce standalone FeRAMs, as well as specialized chips (e.g. chips for smart cards) with embedded FeRAMs within. Fujitsu produces devices for Ramtron. Since at least 2001 Texas Instruments has collaborated with Ramtron to develop FeRAM test chips in a modified 130 nm process. In the fall of 2005 Ramtron reported that they were evaluating prototype samples of an 8 megabit FeRAM manufactured using Texas Instruments' FeRAM process. Fujitsu and Seiko-Epson were in 2005 collaborating in the development of a 180 nm FeRAM process. FeRAM research projects have also been reported at Samsung, Matsushita, Oki, Toshiba, Infineon, Hynix, Symetrix, Cambridge University, University of Toronto and the Interuniversity Microelectronics Centre (IMEC, Belgium).Conventional DRAM consists of a grid of small capacitors and their associated wiring and signaling transistors. Each storage element, a cell, consists of one capacitor and one transistor, a so-called "1T-1C" device. DRAM cells scale directly with the size of the semiconductor fabrication process being used to make it. For instance, on the 90 nm process used by most memory providers to make DDR2 DRAM, the cell size is 0.22 m , which includes the capacitor, transistor, wiring, and some amount of "blank space" between the various parts it appears 35% utilization is typical, leaving 65% of the space wasted.Data in a DRAM is stored as the presence or lack of an electrical charge in the capacitor, with the lack of charge generally representing "0". Writing is accomplished by activating the associated control transistor, draining the cell to write a "0", or sending current into it from a supply line if the new value should be "1". Reading is similar in nature; the transistor is again activated, draining the charge to a sense amplifier. If a pulse of charge is noticed in the amplifier the cell held a charge and thus reads "1", the lack of such a pulse indicates a "0". Note that this process is destructive, once the cell has been read, if it did hold a "1" it must be re-charged to that value again. Since a cell loses its charge after some time due to leak currents, it needs to be actively refreshed at intervals.The 1T-1C storage cell design in an FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor. In a DRAM cell capacitor a linear dielectric is used whereas in an FeRAM cell capacitor the dielectric structure includes ferroelectric material, typically lead zirconate titanate (PZT).A ferroelectric material has a nonlinear relationship between the applied electric field and the apparent stored charge. Specifically, the ferroelectric characteristic has the form of a hysteresis loop, which is very similar in shape to the hysteresis loop of ferromagnetic materials. The dielectric constant of a ferroelectric is typically much higher than that of a linear dielectric because of the effects of semi-permanent electric dipoles formed in the crystal structure of the ferroelectric material. When an external electric field is applied across a dielectric, the dipoles tend to align themselves with the field direction, produced by small shifts in the positions of atoms and shifts in the distributions of electronic charge in the crystal structure. After the charge is removed, the dipoles retain their polarization state. Typically binary "0"s and "1"s are stored as one of two possible electric polarizations in each data storage cell. For example, in the figure a "1" is encoded using the negative remnant polarization "-Pr", and a "0" is encoded using the positive remnant polarization "+Pr".Operationally FeRAM is similar to DRAM. Writing is accomplished by applying a field across the ferroelectric layer by charging the plates on either side of it, forcing the atoms inside into the "up" or "down" orientation (depending on the polarity of the charge), thereby storing a "1" or "0". Reading, however, is somewhat different than in DRAM. The transistor forces the cell into a particular state, say "0". If the cell already held a "0", nothing will happen in the output lines. If the cell held a "1", the re-orientation of the atoms in the film will cause a brief pulse of current in the output as they push electrons out of the metal on the "down" side. The presence of this pulse means the cell held a "1". Since this process overwrites the cell, reading FeRAM is a destructive process, and requires the cell to be re-written if it was changed.Generally the operation of FeRAM is similar to ferrite core memory, one of the primary forms of computer memory in the 1960s. Besides, the ferroelectric effect used in FeRAM was discovered in 1920. In comparison, FeRAM requires far less power to flip the state of the polarity, and does so much faster.

[COOLVEER]

[attachment=2395]

FERROELECTRIC RAM [FRAM]

FEATURES OF FRAM
1.FRAM allows systems to retain information even when power is lost i.e.; non-volatile.
2.The number of write cycles supported by the FRAM components is
nearly unlimited up to 10 billion read/writes.
3.Low power requirements.
4.When an electric field is applied to a ferroelectric crystal,
the central atom moves in the direction of the field.
5.As the atom moves within the crystal, it passes through an energy barrier, causing a charge spike.
6.Internal circuits sense the charge spike and set the memory
If the electric field is removed from the crystal, the central atom stays in position, preserving the state of the memory. This
makes FRAM non-volatile, without any periodic refresh.
7.Once a cell is accessed for a read operation, its data are presented in the form of an anal
Signal to sense amplifier, where they are compared against a reference voltage to find
the logic level.
A ferroelectric memory cell, known as IT- IC (one transistor, one capacitor) structure which is similar to that of DRAM.
The difference is that ferroelectric film is used as its storage capacitor rather than paraelectric material as in DRAM.
Figure above shows memory cell structure, consists of a single ferroelectric capacitor that is connected to a Plateline(PL) at one end and, via an access transistor, to a Bitline(BL) at the other end. Raising the wordline (WL) and hence turning ON the access transistor accesses the cell.

FRAM TECHONOLOGY

When an electric field is applied to a ferroelectric crystal, the central atom moves in the direction of the field.
As the atom moves within the crystal, it passes through an energy barrier,causing a charge spike.
Internal circuits sense the charge spike and set the memory. If the electric field is removed from the crystal, the central atom stays in position, preserving the state of the memory.
This makes FRAM non-volatile, without any periodic refresh

FRAM READ OPERATION


An electric field is applied.

If the atoms are near the cube "floors" and the electric field pushes them to the top, the cell gives off a current pulse.
This pulse, representing a stored 1 or 0, is detected by a sense amplifier. If the atoms are already near their cubes' "ceilings," they don't budge when the field is applied and the cell gives off a smaller pulse.
Reading an FRAM cell destroys the data stored in its capacitor. So after the bit is read, the sense amplifier writes the data back into the cell, just as in a DRAM.

FRAM WRITE OPERATION

To write a "1" into the memory cell,
the BL is raised to Vdd-
Then the WL is raised to Vdd + Vt.
This allows a full Vdd to appear across the ferroelectric capacitor
At this time the state of ferroelectric is independent of its initial state.
Next, the PL is pulsed, WL stays activated until
the PL is pulled down completely and the BL is driven back to zero.
The final state of the capacitor is a negative charge state S1.


To write a "0" into the cell


the BL is driven to 0V prior to activating the WL.
The rest of the operation is similar to that of writing a "1
The written data is held in the cell even though the selection of the wordline is changed to non selected state (i.e. transistor is OFF), so it is nonvolatile.

FRAM AS RAM AND ROM

The key advantage to FRAM over DRAM is what happens between the read and write cycles. In DRAM, every cell must be periodically read and then re-written, a process known as refresh..
In contrast, FRAM only requires power when actually reading or writing a cell. The vast majority of power used in DRAM is used for refresh power usage about 99% lower than DRAM.

ADVANTAGES
* FRAM allows systems to retain information even when power is lost, without resorting to batteries, EEPROM, or flash.
* Access times are the same as for standard SRAM, so there's no delay-at-write access as there is for EEPROM or flash.
* Low power consumption, low voltage operation and high write endurance make it superior than other non-volatile memories like EEPROM & FLASH.
* It is less expensive than magnetic memories.

DISADVANTAGES
Present high cost.
Low density compared to DRAM & SRAM.
FUTURE OF FRAM
Increased memory capacity
High density, to operate under very high temperatures.
Combine FRAM with other logic technologies to offer more enhanced devices.
APPLICATIONS
Personal digital assistants (PDAs), handheld phones, power meters, and smart card, and in security systems
SMART CARDS USING FRAM
Dial a connection on a mobile telephone and be charged on a per-call basis
Establish your identity when logging on to an Internet access provider or to an online bank
Pay for parking at parking meters or to get on subways, trains, or buses
Give hospitals or doctors personal data without filling out a form
Make small purchases at electronic stores on the Web (a kind of cybercash)
Buy gasoline at a gasoline station

CONCLUSION
Ferroelectric memories are superior to EPROM s & Flash memories
in terms of write access time & overall power consumption.Two eg: of
such applications are contactless smart cards & digital cameras.
Future personal wireless connectivity applications that are battery
driven will demand large amounts of non volatile storage to retain
accessed internet webpages, contain compressed video, voice and
data. The density and energy efficiency of writing data to memory
would seem to indicate that ferroelectric memory will play a major role
in these types of consumer products.

[itsmehanoop]

[attachment=5735]

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FRAM

INTRODUCTION:

A ferroelectric memory cell consists of a ferroelectric capacitor and a MOS transistor. Its construction is similar to the storage cell of a DRAM. The difference is in the dielectric properties of the material between the capacitor's electrodes. This material has a high dielectric constant and can be polarized by an electric field. The polarisation remains until it gets reversed by an opposite electrical field. This makes the memory non-volatile. Note that ferroelectric material, despite its name, does not necessarily contain iron. The most well-known ferroelectric substance is BaTiO3.

A Ferroelectric memory cell consists of a ferroelectric capacitor and a MOS transistor. Its construction is similar to the storage cell of a DRAM. The difference is in the dielectric properties of the material between the capacitor's electrodes. This material has a high dielectric constant and can be polarized by an electric field. The polarisation remains until it gets reversed by an opposite electrical field. This makes the memory non-volatile.Data is read by applying an electric field to the capacitor. If this switches the cell into the opposite state (flipping over the electrical dipoles in the ferroelectric material) then more charge is moved than if the cell was not flipped. This can be detected and amplified by sense amplifiers. Reading destroys the contents of a cell which must therefore be written back after a read. This is similar to the precharge operation in DRAM, though it only needs to be done after a read rather than periodically as with DRAM refresh.

FRAM is found mainly in consumer devices and because of its low power requirements, could also be used in devices that only need to activate for brief periods. FRAM allows systems to retain information even when power is lost, without resorting to batteries, EEPROM, or flash. Access times are the same as for standard SRAM, so there's no delay-at-write access as there is for EEPROM or flash. In addition, the number of write cycles supported by the FRAM components is nearly unlimited up to 10 billion read/writes. FRAM combines the advantages of SRAM - writing is roughly as fast as reading, and EPROM - non-volatility and in-circuit programmability
FRAM Technology

When an electric field is applied to a ferroelectric crystal, the central atom moves in the direction of the field. As the atom moves within the crystal, it passes through an energy barrier, causing a charge spike. Internal circuits sense the charge spike and set the memory. If the electric field is removed from the crystal, the central atom stays in position, preserving the state of the memory. Therefore, the FRAM memory needs no periodic refresh and when power fails FRAM memory retains its data. It's fast, and doesn't wear out!

To increase the memory capacity, the cell size must always be reduced, and the design, process, and materials have been improved aggressively for this purpose. ferroelectric RAM products (FRAMs) are the most advanced of the flash challengers. The pioneer, Ramtron International Corp. (Colorado Springs, Colo.), has been selling FRAM chips since 1992. Their memory capacities are low, however, the largest being 256Kb still a small fraction of the multimegabit chips offered by the major flash memory makers. In current commercial FRAMs, the interconnects that page link individual transistors into circuits are 0.5 m wide and operate at 3 V. Narrower interconnects are desirable so that memory cells may be made smaller and be packed in greater numbers onto an IC. Ramtron's FRAMs are made by Fujitsu Ltd., Tokyo, which also sells its own FRAM products, mostly as embedded memory in microcontrollers and smart cards.

The biggest hurdle for FRAM developers is to advance the manufacturing technology to smaller geometries and lower voltages. R&D at Ramtron is aiming at 0.35- m interconnect widths and 1.8-V operation. And last November, Texas Instruments Inc. (Dallas) announced that it had built a 64Mb FRAM in a standard 0.13- m CMOS process, using technology licensed from Ramtron.

[radhey shyam]

SUBMITTED BY
SANGEETHA S

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[attachment=15160]
ABSTRACT
FRAM is a type of non-volatile read/write random access semiconductor memory. FRAM combines the advantages of SRAM writing is roughly as fast as reading, and EPROM non-volatility and in-circuit programmability. FRAM (ferroelectric RAM) is a random access memory that combines the fast read and write access of dynamic RAM (DRAM) - the most common kind of personal computer memory - with the ability to retain data when power is turned off (as do other non-volatile memory devices such as ROM and flash memory). Because FRAM is not as dense (can not store as much ata in the same space) as DRAM and SRAM, it is not likely replace these technologies. It is fast memory with a very low power requirement, it is expected to have many applications in small consumer devices such as personal digital assistants (PDA), handheld phones, power meters, and smart card, and in security systems. FRAM is faster than flash memory. It is also expected to replace EEPROM and SRAM for some applications and to become a key component in future wireless products.
INTRODUCTION:
A ferroelectric memory cell consists of a ferroelectric capacitor and a MOS transistor. Its construction is similar to the storage cell of a DRAM. The difference is in the dielectric properties of the material between the capacitor's electrodes. This material has a high dielectric constant and can be polarized by an electric field. The polarisation remains until it gets reversed by an opposite electrical field. This makes the memory non-volatile. Note that ferroelectric material, despite its name, does not necessarily contain iron. The most well-known ferroelectric substance is BaTiO3.
A Ferroelectric memory cell consists of a ferroelectric capacitor and a MOS transistor. Its construction is similar to the storage cell of a DRAM. The difference is in the dielectric properties of the material between the capacitor's electrodes. This material has a high dielectric constant and can be polarized by an electric field. The polarisation remains until it gets reversed by an opposite electrical field. This makes the memory non-volatile.
Data is read by applying an electric field to the capacitor. If this switches the cell into the opposite state (flipping over the electrical dipoles in the ferroelectric material) then more charge is moved than if the cell was not flipped. This can be detected and amplified by sense amplifiers. Reading destroys the contents of a cell which must therefore be written back after a read. This is
similar to the precharge operation in DRAM, though it only needs to be done after a read rather than periodically as with DRAM refresh.
FRAM is found mainly in consumer devices and because of its low power requirements, could also be used in devices that only need to activate for brief periods. FRAM allows systems to retain information even when power is lost, without resorting to batteries, EEPROM, or flash. Access times are the same as for standard SRAM, so there's no delay-at-write access as there is for EEPROM or flash. In addition, the number of write cycles supported by the FRAM components is nearly unlimited up to 10 billion read/writes. FRAM combines the advantages of SRAM - writing is roughly as fast as reading, and EPROM - non-volatility and in-circuit programmability

[bmkrishna441]

[attachment=5948]

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Introduction

Why FRAM

Short programming time
Low power consumption
Non-volatile memory

TECHNOLOGY

Consists of a CMOS technology with added layers on top for ferroelectric capacitors
Has at least one ferroelectric capacitor to store the binary data
One or two transistors that provide access to the capacitor