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Geometric Program based analog circuit sizing in sub-micron technology
#1

An improvised MOS transistor model suitable for
Geometric Program based analog circuit sizing in
sub-micron technology


A special monomial form of the device model is required by the Geometric program. This article describes the work done in identifying the sources of inaccuracy in this basic model. The strict monomial form has been relaxed. the sizing problem is solved as a series of geometric programs instead of solving it considering as single entity. a folded-cascode op-amp sizing example is used to describe the efficiency of the program. Thus the methods to improve accuracy of performance prediction for geometric program based analog design in submicron regime is discussed here.

Analog circuit sizing involves the determination of the device sizes and biases of a given circuit in order to satisfy the laid down specifications. The area of geometric programming for automated analog sizing has been witnessing considerable research and it also gives desirable properties of a sizing engine such as speed, global optima without user inervention. op-amps, PLL,
ADC and several other circuits have been optimised using this technique.

get the report pdf here:
http://mediafire?wd9t57z4vkiz6ph
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