project report on c-mos full adder for energy efficient arithetic appications ....etc

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could you please send me the lex program to specify decimal numbers
....etc

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import java.applet.*;
import java.awt.*;
import java.awt.event.*;
import java.awt.Choice.*;
//
public class Awte extends Applet implements TextListener,ActionListener
{
int a,b,c;
String s;
TextField f1,f2,f3;
Label l1,l2,l3;
Button Add,Sub,Mul,Div;
public void init()
{
//setBackground(Color.green);
setForeground(Color.red);
l1=new Label(First number);
l2=new Label(Second number);
l3=new Label(Result);
f1=new TextField(10);
f2=new TextField(20);
f3=new T ....etc

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to get information about the topic improved design of high performance parallel decimal multipliers full report ppt and related topic refer the page link bellow

http://seminarsprojects.net/Thread-improved-design-of-high-performance-parallel-decimal-multipliers

http://seminarsprojects.net/Thread-high-performance-dsp-architectures--3878

http://seminarsprojects.net/Thread-high-performance-dsp-architectures--1908 ....etc

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Improved Design of High-Performance Parallel Decimal Multipliers
The efficient implementations of parallel decimal multipliers is demanded by the new generation of high-performance decimal floating-point units (DFUs). The architectures of two parallel decimal multipliers is described in this chapter. signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples is used to perform the parallel generation of partial products. The partial products are th ....etc

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pnhb ....etc

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to get information about the topic vlsi architecture of arithmetic coder used in spiht full report ppt and related topic refer the page link bellow

http://seminarsprojects.net/Thread-vlsi-architecture-of-arithmetic-coder-used-in-spiht-report

http://seminarsprojects.net/Thread-vlsi-architecture-of-arithmetic-coder-used-in-spiht-pdf ....etc

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High-Speed VLSI Arithmetic Units: Adders and Multipliers


Introduction

Digital computer arithmetic is an aspect of logic design with the objective of developing
appropriate algorithms in order to achieve an efficient utilization of the available hardware .
Given that the hardware can only perform a relatively simple and primitive set of Boolean
operations, arithmetic operations are based on a hierarchy of operations that are built upon the
simple ones. Since ultimately, speed, power and chip area ar ....etc

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parallel decimal multipliers vhdl code

Abstract

Decimal hardware arithmetic units have recently regained popularity, as there is now a high demand for high performance decimal arithmetic. We propose a novel method for carry-free addition of decimal numbers, where each equally weighted decimal digit pair of the two operands is partitioned into two weighted bit-sets. The arithmetic values of these bit-sets are evaluated, in parallel, for fast computation of the transfer digit and interim sum. In the proposed fully redundant adder (VS semi-redun ....etc

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Abstract
In this paper, we review the logical effort model presented in . Based on the HSPICE simulation results using 0.18/Jm, CMOS technology as applied to logic blocks used in arithmetic circuits; we analyze the efficiency of the model and also present modifications that include modeling of wire delay. We propose a new model for logical effort that will better fit the behavior of these blocks. The results are applicable for evaluation of arithmetic units as well as for development of new arithmetic algorithms. Our ultimate objective is ....etc

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