I am looking for a free implementation of an HDLC controller using VHDL.
If you could direct me as to where to look for that I would greatly appreciate it. ....etc

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adaptive viterbi decoder m tech thesis vhdl code

ABSTRACT:

A new trend in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit environmental requirements. Wireless networks usually employ sophisticated Forward Error Correction (FEC) techniques such as Viterbi Algorithm to combat with the channel distortion effects such as multipath fading and intersymbol interference. Viterbi algorithm is employed in wireless communication to decode the Convolution codes; these are the class ....etc

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median filter vhdl code for image

Abstract

In this paper an efficient method for removing noise as well as preserving the edge from corrupted image is presented here. In the signal transmission, the image signal can be corrupted by noise and the blurred image be the result. Impulse noise is caused by malfunctioning pixels in camera sensors, faulty memory locations in
hardware, or transmission in a noisy channel. For instance two common types of impulse noise are the salt-and-pepper noise and the random-valued noise. For images corrupted by sa ....etc

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Dear Sir,
Iam looking for dwt vhdl code..to be implemented in two dimentional 2D DWT in image compression topic.If there is an application on traditional convolution type DWT such as CDF 9/7 or the Lifting scheme DWT of this type CDF 9/7, or any example type and also the SPIHT implementation in VHDL.
Thanks and regards ....etc

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library IEE;
use IEE.STD_LOGIC_1164.ALL;
use IEE.NUMERIC_STD.ALL;

entity CSA is
Port ( x : in unsigned (3 downto 0);
y : in unsigned (3 downto 0);
z : in unsigned (3 downto 0);
cout : out std_logic;
s : out unsigned (4 downto 0)
);
end CSA;

architecture Behavioral of CSA is

component fulladder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end component;

signal c1,s1,c2 : unsigned (3 downto 0) := (others => '0');

begin

fa_inst10 : fulladder port ma ....etc

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Hi,
Can u send me the vhdl code for implementation of hamming code ....etc

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To get full information or details of vhdl code for water level controller please have a look on the pages

http://seminarsprojects.net/Thread-water-level-controller

http://seminarsprojects.net/Thread-automatic-water-level-controller

http://seminarsprojects.net/Thread-automatic-water-level-monitoring-controller-using-microcontroller-circuit

http://seminarsprojects.net/Thread-simple-automatic-water-level-controller

if you again feel trouble on vhdl code for water level controller please reply in that page and ask specific fields in vhdl co ....etc

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i want Manchester adder's particular circuit and vhdl structural,data flow and behavioural method program as erlier as possible.. ....etc

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High-Level Data Link Control (HDLC)

High-Level Data Link Control (HDLC) is a bit-oriented synchronous data page link layer protocol developed by the International Organization for Standardization (ISO). The original ISO standards for HDLC are:
ISO 3309 Frame Structure
ISO 4335 Elements of Procedure
ISO 6159 Unbalanced Classes of Procedure
ISO 6256 Balanced Classes of Procedure
The current standard for HDLC is ISO 13239, which replaces all of those standards.
HDLC provides both connection-or ....etc

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i want to transfer data wirelessly using cpld and ht12e rf module.Can you tell me that how can i interface rf module with fpga using vhdl code ....etc

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