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Reduced Instruction Set Computer (RISC) processor

INTRODUCTION
This project is aimed at designing of a Reduced Instruction Set Computer (RISC) processor using the Verilog Hardware Description Language (HDL). For a long time, programming languages such as C, Pascal & FORTRAN were being used to describe the computer programs that were sequential in nature. Similarly in the digital design field, designers felt the need for a standard language to describe digital circuits. Thus, HDL came into existence. HDL allowed ....etc

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Abstract
Traditionally, common processor augmentation solutions have involved the addition of coprocessors or the datapath integration of custom instructions within extensible processors as Instruction Set Extensions (ISE). Rarely is the hybrid option of using both techniques explored. Much research already exists concerning the identification and selection of custom hardware blocks from hardware/software partitioning techniques, but the question of how to best use this hardware within a user system where both coprocessors and datapath ....etc

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Introduction

Recent and anticipated changes in technology arising from the convergence of communications and computing are truly breathtaking, and have already had a significant impact on many aspects of life. Banking, stock exchanges, air traffic control, telephones, electric power, health care, welfare and education are largely dependent of information technology and telecommunications for their operation. We are moving towards the point where it is possible to assert that everything depends on software ....etc

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