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Title: IEEE Network Simulation Projects on OMNeT 32 - BTechMTechResearch Level
Page Link: IEEE Network Simulation Projects on OMNeT 32 - BTechMTechResearch Level -
Posted By: ranjithmambra
Created at: Thursday 05th of October 2017 05:19:13 AM
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Hi.. Here you can find the topics of latest IEE Network Simulation Projects implemented in tool OMNeT++ 3.2.

1. Minimum Distance Packet Forwarding

This IEE Journal Technology Simulation Project is the simulation of Minimum Distance Packet Forwarding for search application in Network (P2P) using OMNeT++ 3.2 tool. This technique is based on technique published on IEE Transaction paper.

2. Endpoint Admission Control

This IEE Journal Technology Simulation Project is the simulation of Probing Mechanism for Endpoint Admission Control in ....etc

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Title: code for moving object tracking and detecting in verilog or vhdl
Page Link: code for moving object tracking and detecting in verilog or vhdl -
Posted By: pranavpta
Created at: Thursday 17th of August 2017 05:50:14 AM
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Introduction to Video tracking

Video tracking is the process of locating a moving object (or multiple objects) over time using a camera. It has a variety of uses, some of which are: human-computer interaction, security and surveillance, video communication and compression, augmented reality, traffic control, medical imaging and video editing. Video tracking can be a time consuming process due to the amount of data that is contained in video. Adding further to the complexity is the possible need to use object recognition techniques for tracki ....etc

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Title: m tech thesis based on verilog 2012
Page Link: m tech thesis based on verilog 2012 -
Posted By: salimyusuf_vicky
Created at: Thursday 17th of August 2017 04:50:25 AM
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Sir I am PG scholar in VLSI DESIGN and want to know some current and promising topics for thesis using VERILOG HDL.

Thanks ....etc

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Title: vhdl verilog based mini project
Page Link: vhdl verilog based mini project -
Posted By: kamini rajput
Created at: Thursday 05th of October 2017 05:38:16 AM
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to get information about the topic vhdl verilog related topic refer the page link bellow

http://seminarsprojects.net/Thread-digital-design-using-vhdl-and-verilog ....etc

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Title: course viva question for b tech computer science cusat b tech
Page Link: course viva question for b tech computer science cusat b tech -
Posted By: cool_tiger158
Created at: Thursday 05th of October 2017 04:51:38 AM
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BRANCH: COMPUTER SCIENCE AND ENGINEERING

CS 010 405- MICROPROCESSOR SYSTEMS (CS)

Part A

Answer all questions.

Each Question Carries 3 marks

1. What is microprocessor? Give the power supply and Clock frequency of 8085

2. Define instruction cycle, machine cycle and T-state

3. Explain the signals HOLD, READY and SID.

4. What is synchronous data transfer?

5. What is the use of modem control unit in 8251?

Part B

Answer all questions

Each question carries 5 marks

6. Compare CALL and PUSH instructions

7. Difference between memory mapped ....etc

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Title: verilog or vhdl code for low power error tolerant adder
Page Link: verilog or vhdl code for low power error tolerant adder -
Posted By: jishnupr
Created at: Thursday 17th of August 2017 05:12:20 AM
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verilog or vhdl code for low power error tolerant adder

Abstract: Problem statement: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, Error Tolerance (ET), a novel Error-Tolerant Adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain i ....etc

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Title: Engineering Projects for Diploma BE ME BTech MTech Students
Page Link: Engineering Projects for Diploma BE ME BTech MTech Students -
Posted By: barbil
Created at: Thursday 05th of October 2017 04:08:59 AM
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Topics

Abs Computers

Srno. Project Titles
1 Home Appliance Control From Remote System Voice Based
2 Payroll System RFID
3 Real Patient Monitoring System
4 Movie Bookie Using Smart Phone
5 Audio Steganography (No MATLAB)
6 Image Steganography (No MATLAB)
7 PC Based Graph Follower Robot
8 Voice Operated Car
9 SMS Based Railway Reservation System
10 J2ME Based Railway Reservation System
11 Attendance Management System
12 PCB Drilling System
13 Mega Travel Management System
14 Millions of Acres.com
15 Media Player in C#
16 ....etc

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Title: IEEE Project on Network Simulation using OMNeT 32 for MTech and BTech
Page Link: IEEE Project on Network Simulation using OMNeT 32 for MTech and BTech -
Posted By: [email protected]
Created at: Friday 06th of October 2017 02:47:20 PM
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These are the various Network simulation Projects developed in OMNeT++ 3.2 which can be used for M.Tech, B.Tech and M.C.A students. On need of any project source code. Please Contact me.

1. Efficient Routing via Clustering using OMNeT (Type-A)

Basepaper: Efficient Node Search in P2P Using Distributed Spanning Tree ((IJCSIS) International Journal of Computer Science and Information Security,
Vol. 8, No. 3, June 2010)

Peer to Peer (P2P) networks are the important part of the next cohort of Internet, so how ....etc

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Title: vhdl or verilog projects for m tech electronics
Page Link: vhdl or verilog projects for m tech electronics -
Posted By: apratik
Created at: Thursday 05th of October 2017 04:59:37 AM
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suggest me some vhdl or verilog project which can be performed by using fpga ....etc

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Title: vhdl verilog code for discrete wavelet transform
Page Link: vhdl verilog code for discrete wavelet transform -
Posted By: gur@100
Created at: Thursday 17th of August 2017 05:10:52 AM
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To get full information or details of discrete wavelet transform please have a look on the pages

http://seminarsprojects.net/Thread-discrete-wavelet-transform-based-satellite-image-resolution-enhancement

http://seminarsprojects.net/Thread-discrete-wavelet-transform-dwt

if you again feel trouble on discrete wavelet transform please reply in that page and ask specific fields in discrete wavelet transform ....etc

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