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http://seminarsprojects.net/Thread-asynchronous-chips--5393

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INITIALIZATION BASED TEST PATTERN GENERATION FOR ASYNCHRONOUS CIRCUIS

1.0 INTRODUCTION
An Asynchronous Circuit is a circuit in which the parts are largely autonomous. The circuit is not governed by a clock circuit or global clock signal, but instead needs to wait only for the signals that indicate the completion of the instructions and operations. The asynchronous circuits provides a promising technology for low-power, high performance, low emission and hig ....etc

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VLSI based asynchronous Receiver and Transmitter

The aim of this project is to design and implement an asynchronous receiver,
transmitter using verilog hardware description language. In this project we have
used serial mode of transmission because in parallel mode of transmission we need
n number of cable to transmit n bits of data. The following features mainly
distinguishes our project from other similar devices
- full duplex operation
- standard data format
- even or odd parity
- parity error ....etc

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DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIFO FOR EMBEDDED APPLICATIONS

A FIFO is used as a First In-First Out memory buffer between two asynchronous systems with simultaneous write and read access to and from the FIFO, these accesses being independent of one another. Data written into a FIFO is sequentially read out in a pipelined manner, such that the first data written into a FIFO will be the first data read out of the FIFO.

FIFO status flag outputs are a function of the comparison of the respective write and read pointers. A FIFO w ....etc

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1. INTRODUCTION

Computer chips of today are synchronous. They contain a main clock, which controls the timing of the entire chips. There are problems, however, involved with these clocked designs that are common today.

One problem is speed. A chip can only work as fast as its slowest component. Therefore, if one part of the chip is especially slow, the other parts of the chip are forced to sit idle. This wasted computed time is obviously detrimental to the speed of the chip.

....etc

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Cooperative Asynchronous Multichannel MAC: Design, Analysis, and Implementation
Luo, T. Motani, M. Srinivasan, V. Nat. Univ. of Singapore, Singapore;
This paper appears in: Mobile Computing, IEE Transactions on Publication

Abstract
Medium access control (MAC) protocols have been studied under different contexts for decades. In decentralized contexts, transmitter-receiver pairs make independent decisions, which are often suboptimal due to insufficient knowledge about the communication environment. In this paper, we introduce dis ....etc

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Breaking the bounds of the clock on a processor may seem a daunting task to those brought up through a typical engineering program. Without the clock, how do you organize the chip and know when you have the correct data or instruction? We may have to take this task on very soon.
Clock speeds are now on the gigahertz range and there is not much room for speedup before physical realities start to complicate things. With a gigahertz powering a chip, signals barely have enough time to make it across the chip before the next clo ....etc

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Abstract:
The number of industry applications in which induction motors are fed by static frequency inverters is growing fast and, although much has already been done within this field, there is still a lot to be studied/understood regarding such applications. The advance of variable speed drives systems engineering increasingly leads to the need of specific technical guidance provision by electrical machines and drives manufacturers, In this paper we have studied and developed a simulink model with PWM inverter and find out the variou ....etc

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ABSTRACT
Chameleon chips are chips whose circuitry can be tailored specifically for the problem at hand. Chameleon chips would be an extension of what can already be done with field-programmable gate arrays (FPGAS). An FPGA is covered with a grid of wires. At each crossover, there's a switch that can be semipermanently opened or closed by sending it a special signal. Usually the chip must first be inserted in a little box that sends the programming signals. But now, labs in Europe, Japan, and the U.S. are developing techniq ....etc

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1. INTRODUCTION

Computer chips of today are synchronous. They contain a main clock, which controls the timing of the entire chips. There are problems, however, involved with these clocked designs that are common today.

One problem is speed. A chip can only work as fast as its slowest component. Therefore, if one part of the chip is especially slow, the other parts of the chip are forced to sit idle. This wasted computed time is obviously detrimental to the speed of the chip.

New problems with speeding up a clo ....etc

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